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[InstrRef] Preserve debug instr num in aarch64-ldst-opt.
The aarch64-ldst-opt pass tries to merge two load instructions (LDR*) to a load pair instruction (LDP*). When merging the instructions, there is a case where one of the loads would have to also be sign extended. In either case, (sign extend or not), the pass needs to preserve the debug-instr-number from the original loads to the load pair instruction to make sure debug info isn't loast in the case where instruction referencing is being used. This patch addresses that problem.
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‎llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

Lines changed: 138 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -964,6 +964,32 @@ static void updateDefinedRegisters(MachineInstr &MI, LiveRegUnits &Units,
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Units.addReg(MOP.getReg());
965965
}
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967+
/// This function will add a new entry into the debugValueSubstitutions table
968+
/// when two instruction have been merged into a new one represented by \p
969+
/// MergedInstr.
970+
static void addDebugSubstitutionsToTable(MachineFunction *MF,
971+
unsigned InstrNumToSet,
972+
MachineInstr &OriginalInstr,
973+
MachineInstr &MergedInstr) {
974+
975+
// Figure out the Operand Index of the destination register of the
976+
// OriginalInstr in the new MergedInstr.
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auto Reg = OriginalInstr.getOperand(0).getReg();
978+
unsigned OperandNo = 0;
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bool RegFound = false;
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for (const auto Op : MergedInstr.operands()) {
981+
if (Op.getReg() == Reg) {
982+
RegFound = true;
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break;
984+
}
985+
OperandNo++;
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}
987+
988+
if (RegFound)
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MF->makeDebugValueSubstitution({OriginalInstr.peekDebugInstrNum(), 0},
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{InstrNumToSet, OperandNo});
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}
992+
967993
MachineBasicBlock::iterator
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AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator Paired,
@@ -1226,6 +1252,79 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
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.addImm(0)
12271253
.addImm(31);
12281254
(void)MIBSXTW;
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// In the case of a sign-extend, where we have something like:
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// debugValueSubstitutions:[]
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// $w1 = LDRWui $x0, 1, debug-instr-number 1
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// DBG_INSTR_REF !7, dbg-instr-ref(1, 0), debug-location !9
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// $x0 = LDRSWui $x0, 0, debug-instr-number 2
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// DBG_INSTR_REF !8, dbg-instr-ref(2, 0), debug-location !9
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// It will be converted to:
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// debugValueSubstitutions:[]
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// $w0, $w1 = LDPWi $x0, 0
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// $w0 = KILL $w0, implicit-def $x0
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// $x0 = SBFMXri $x0, 0, 31
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// DBG_INSTR_REF !7, dbg-instr-ref(1, 0), debug-location !9
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// DBG_INSTR_REF !8, dbg-instr-ref(2, 0), debug-location !9
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// We want the final result to look like:
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// debugValueSubstitutions:
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// - { srcinst: 1, srcop: 0, dstinst: 4, dstop: 1, subreg: 0 }
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// - { srcinst: 2, srcop: 0, dstinst: 3, dstop: 0, subreg: 0 }
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// $w0, $w1 = LDPWi $x0, 0, debug-instr-number 4
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// $w0 = KILL $w0, implicit-def $x0
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// $x0 = SBFMXri $x0, 0, 31, debug-instr-number 3
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// DBG_INSTR_REF !7, dbg-instr-ref(1, 0), debug-location !9
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// DBG_INSTR_REF !8, dbg-instr-ref(2, 0), debug-location !9
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// $x0 is where the final value is stored, so the sign extend (SBFMXri)
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// instruction contains the final value we care about we give it a new
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// debug-instr-number 3. Whereas, $w1 contains the final value that we care
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// about, therefore the LDP instruction is also given a new
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// debug-instr-number 4. We have to add these subsitutions to the
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// debugValueSubstitutions table. However, we also have to ensure that the
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// OpIndex that pointed to debug-instr-number 1 gets updated to 1, because
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// $w1 is the second operand of the LDP instruction.
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if (I->peekDebugInstrNum()) {
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// If I is the instruction which got sign extended and has a
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// debug-instr-number, give the SBFMXri instruction a new
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// debug-instr-number, and update the debugValueSubstitutions table with
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// the new debug-instr-number and OpIndex pair. Otherwise, give the Merged
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// instruction a new debug-instr-number, and update the
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// debugValueSubstitutions table with the new debug-instr-number and
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// OpIndex pair.
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unsigned NewInstrNum;
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if (DstRegX == I->getOperand(0).getReg()) {
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NewInstrNum = MIBSXTW->getDebugInstrNum();
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addDebugSubstitutionsToTable(MBB->getParent(), NewInstrNum, *I,
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*MIBSXTW);
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} else {
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NewInstrNum = MIB->getDebugInstrNum();
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addDebugSubstitutionsToTable(MBB->getParent(), NewInstrNum, *I, *MIB);
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}
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}
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if (Paired->peekDebugInstrNum()) {
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// If Paired is the instruction which got sign extended and has a
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// debug-instr-number, give the SBFMXri instruction a new
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// debug-instr-number, and update the debugValueSubstitutions table with
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// the new debug-instr-number and OpIndex pair. Otherwise, give the Merged
1313+
// instruction a new debug-instr-number, and update the
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// debugValueSubstitutions table with the new debug-instr-number and
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// OpIndex pair.
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unsigned NewInstrNum;
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if (DstRegX == Paired->getOperand(0).getReg()) {
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NewInstrNum = MIBSXTW->getDebugInstrNum();
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addDebugSubstitutionsToTable(MBB->getParent(), NewInstrNum, *Paired,
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*MIBSXTW);
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} else {
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NewInstrNum = MIB->getDebugInstrNum();
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addDebugSubstitutionsToTable(MBB->getParent(), NewInstrNum, *Paired,
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*MIB);
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}
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}
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LLVM_DEBUG(dbgs() << " Extend operand:\n ");
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LLVM_DEBUG(((MachineInstr *)MIBSXTW)->print(dbgs()));
12311330
} else if (Opc == AArch64::LDR_ZXI || Opc == AArch64::STR_ZXI) {
@@ -1239,6 +1338,45 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
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MOp1.setReg(AArch64::Q0 + (MOp1.getReg() - AArch64::Z0));
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LLVM_DEBUG(((MachineInstr *)MIB)->print(dbgs()));
12411340
} else {
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// In the case that the merge doesn't result in a sign-extend, if we have
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// something like:
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// debugValueSubstitutions:[]
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// $x1 = LDRXui $x0, 1, debug-instr-number 1
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// DBG_INSTR_REF !13, dbg-instr-ref(1, 0), debug-location !11
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// $x0 = LDRXui killed $x0, 0, debug-instr-number 2
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// DBG_INSTR_REF !14, dbg-instr-ref(2, 0), debug-location !11
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// It will be converted to:
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// debugValueSubstitutions: []
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// $x0, $x1 = LDPXi $x0, 0
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// DBG_INSTR_REF !12, dbg-instr-ref(1, 0), debug-location !14
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// DBG_INSTR_REF !13, dbg-instr-ref(2, 0), debug-location !14
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// We want the final result to look like:
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// debugValueSubstitutions:
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// - { srcinst: 1, srcop: 0, dstinst: 3, dstop: 1, subreg: 0 }
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// - { srcinst: 2, srcop: 0, dstinst: 3, dstop: 0, subreg: 0 }
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// $x0, $x1 = LDPXi $x0, 0, debug-instr-number 3
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// DBG_INSTR_REF !12, dbg-instr-ref(1, 0), debug-location !14
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// DBG_INSTR_REF !12, dbg-instr-ref(2, 0), debug-location !14
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1364+
// Here all that needs to be done is, that the LDP instruction needs to be
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// updated with a new debug-instr-number, we then need to add entries into
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// the debugSubstitutions table to map the old instr-refs to the new ones.
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1368+
// Assign new DebugInstrNum to the Paired instruction.
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if (I->peekDebugInstrNum()) {
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unsigned NewDebugInstrNum = MIB->getDebugInstrNum();
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addDebugSubstitutionsToTable(MBB->getParent(), NewDebugInstrNum, *I,
1372+
*MIB);
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}
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if (Paired->peekDebugInstrNum()) {
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unsigned NewDebugInstrNum = MIB->getDebugInstrNum();
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addDebugSubstitutionsToTable(MBB->getParent(), NewDebugInstrNum, *Paired,
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*MIB);
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}
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LLVM_DEBUG(((MachineInstr *)MIB)->print(dbgs()));
12431381
}
12441382
LLVM_DEBUG(dbgs() << "\n");

‎llvm/test/CodeGen/AArch64/aarch64-ldst-opt-instr-ref.mir

Lines changed: 91 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,91 @@
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# RUN: llc -mtriple=aarch64-unknown-linux-gnu -o - %s -run-pass=aarch64-ldst-opt | FileCheck %s
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3+
# This testcase was obtained by looking at FileCheck.cpp and reducing it down via llvm-reduce
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# The aarch64-ldst-opt pass tries to merge load instructions from LDR* to a load pair or LDP* instruction, in such a case, we must ensure that the debug-instr-number is properly preserved for instruction referencing.
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# Check that in the case of a sign extend, the debug instruction number is transferred to the sign extend instruction (SBFMXri in this case), whereas the LDP instruction gets the other debug instruction number for the load that doesn't get sign extended.
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# CHECK-LABEL: name: _ZNK4llvm7Pattern5matchENS_9StringRefERKNS_9SourceMgrE
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# CHECK: debugValueSubstitutions:
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# CHECK-NEXT: - { srcinst: [[DBG_INSTR_NUM1:[0-9+]]], srcop: [[DBG_INSTR_OP1:[0-9+]]], dstinst: [[DBG_INSTR_NUM2:[0-9+]]], dstop: 1, subreg: 0 }
12+
# CHECK-NEXT: - { srcinst: [[DBG_INSTR_NUM3:[0-9+]]], srcop: [[DBG_INSTR_OP2:[0-9+]]], dstinst: [[DBG_INSTR_NUM4:[0-9+]]], dstop: 0, subreg: 0 }
13+
14+
# CHECK: $w[[REG1:[0-9+]]], renamable $w[[REG2:[0-9+]]] = LDPWi renamable $x[[REG1]], 0, debug-instr-number [[DBG_INSTR_NUM2]]
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# CHECK-NEXT: $w[[REG1]] = KILL $w[[REG1]], implicit-def $x[[REG1]]
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# CHECK-NEXT: $x[[REG1]] = SBFMXri $x[[REG1]], 0, 31, debug-instr-number [[DBG_INSTR_NUM4]]
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# CHECK-NEXT: DBG_INSTR_REF !{{[0-9+]}}, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 64, 64), dbg-instr-ref([[DBG_INSTR_NUM1]], [[DBG_INSTR_OP1]]), debug-location !{{[0-9+]}}
18+
# CHECK-NEXT: DBG_INSTR_REF !7, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 64, 32), dbg-instr-ref([[DBG_INSTR_NUM3]], [[DBG_INSTR_OP2]]), debug-location !{{[0-9+]}}
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# Check that in the case there is no sign extend, the LDP instruction gets a new debug instruction number and both the DBG_INSTR_REFs use the new instruction number.
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# CHECK-LABEL: name: _ZNK4llvm7Pattern5matchENS_9StringRefERKNS_9SourceMgrE2
23+
# CHECK: debugValueSubstitutions:
24+
# CHECK-NEXT: - { srcinst: [[DBG_INSTR_NUM5:[0-9+]]], srcop: [[DBG_INSTR_OP3:[0-9+]]], dstinst: [[DBG_INSTR_NUM6:[0-9+]]], dstop: 1, subreg: 0 }
25+
# CHECK-NEXT: - { srcinst: [[DBG_INSTR_NUM7:[0-9+]]], srcop: [[DBG_INSTR_OP4:[0-9+]]], dstinst: [[DBG_INSTR_NUM6]], dstop: 0, subreg: 0 }
26+
27+
# CHECK: renamable $x[[REG3:[0-9+]]], renamable $x[[REG4:[0-9+]]] = LDPXi renamable $x[[REG3]], 0, debug-instr-number [[DBG_INSTR_NUM6]]
28+
# CHECK-NEXT: DBG_INSTR_REF !12, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 64, 64), dbg-instr-ref([[DBG_INSTR_NUM5]], [[DBG_INSTR_OP3]]), debug-location !14
29+
# CHECK-NEXT: DBG_INSTR_REF !12, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 64, 32), dbg-instr-ref([[DBG_INSTR_NUM7]], [[DBG_INSTR_OP4]]), debug-location !14
30+
31+
--- |
32+
define i64 @_ZNK4llvm9StringRef4sizeEv(ptr readonly captures(none) %this) local_unnamed_addr #0 {
33+
entry:
34+
%Length = getelementptr i8, ptr %this, i64 8
35+
%0 = load i64, ptr %Length, align 4
36+
ret i64 %0
37+
}
38+
define ptr @_ZNK4llvm9StringRef4dataEv(ptr readonly captures(none) %this) local_unnamed_addr #0 {
39+
entry:
40+
%0 = load ptr, ptr %this, align 8
41+
ret ptr %0
42+
}
43+
define void @_ZNK4llvm7Pattern5matchENS_9StringRefERKNS_9SourceMgrE(ptr readonly captures(none) %agg.result) local_unnamed_addr !dbg !3 {
44+
%call1541 = load volatile ptr, ptr null, align 4294967296, !dbg !9
45+
%FullMatch.sroa.1.0.agg.result.sroa_idx = getelementptr inbounds nuw i8, ptr %agg.result, i64 8
46+
ret void
47+
}
48+
define void @_ZNK4llvm7Pattern5matchENS_9StringRefERKNS_9SourceMgrE2(ptr readonly captures(none) %agg.result) local_unnamed_addr !dbg !10 {
49+
%call1541 = load volatile ptr, ptr null, align 4294967296, !dbg !11
50+
%FullMatch.sroa.1.0.agg.result.sroa_idx = getelementptr inbounds nuw i8, ptr %agg.result, i64 8
51+
ret void
52+
}
53+
!llvm.module.flags = !{!0}
54+
!llvm.dbg.cu = !{!1}
55+
!0 = !{i32 2, !"Debug Info Version", i32 3}
56+
!1 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !2, isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, sdk: "MacOSX15.3.sdk")
57+
!2 = !DIFile(filename: "/Users/shubhamrastogi/Development/llvm-project-instr-ref/llvm-project/llvm/lib/FileCheck/FileCheck.cpp", directory: "/Users/shubhamrastogi/Development/llvm-project-instr-ref/llvm-project/build-baseline-stage2", checksumkind: CSK_MD5, checksum: "ac1d2352ab68b965fe7993c780cf92d7")
58+
!3 = distinct !DISubprogram(scope: null, type: !4, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !6)
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!4 = distinct !DISubroutineType(types: !5)
60+
!5 = !{}
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!6 = !{!7}
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!7 = !DILocalVariable(name: "FullMatch", scope: !3, line: 1152, type: !8)
63+
!8 = distinct !DICompositeType(tag: DW_TAG_class_type, size: 128, identifier: "_ZTSN4llvm9StringRefE")
64+
!9 = !DILocation(line: 0, scope: !3)
65+
!10 = distinct !DISubprogram(scope: null, type: !4, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !12)
66+
!11 = !DILocation(line: 0, scope: !10)
67+
!12 = !{!13}
68+
!13 = !DILocalVariable(name: "FullMatch", scope: !10, line: 1152, type: !14)
69+
!14 = distinct !DICompositeType(tag: DW_TAG_class_type, size: 128, identifier: "_ZTSN4llvm9StringRefE")
70+
71+
name: _ZNK4llvm9StringRef4sizeEv
72+
---
73+
name: _ZNK4llvm9StringRef4dataEv
74+
...
75+
name: _ZNK4llvm7Pattern5matchENS_9StringRefERKNS_9SourceMgrE
76+
debugValueSubstitutions: []
77+
body: |
78+
bb.0 (%ir-block.0):
79+
renamable $w1 = LDRWui renamable $x0, 1, debug-instr-number 1 :: (load (s64) from %ir.FullMatch.sroa.1.0.agg.result.sroa_idx, align 1)
80+
DBG_INSTR_REF !7, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 64, 64), dbg-instr-ref(1, 0), debug-location !9
81+
renamable $x0 = LDRSWui killed renamable $x0, 0, debug-instr-number 2 :: (load (s64) from %ir.agg.result)
82+
DBG_INSTR_REF !7, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 64, 32), dbg-instr-ref(2, 0), debug-location !9
83+
...
84+
name: _ZNK4llvm7Pattern5matchENS_9StringRefERKNS_9SourceMgrE2
85+
debugValueSubstitutions: []
86+
body: |
87+
bb.0 (%ir-block.0):
88+
renamable $x1 = LDRXui renamable $x0, 1, debug-instr-number 1 :: (load (s64) from %ir.FullMatch.sroa.1.0.agg.result.sroa_idx, align 1)
89+
DBG_INSTR_REF !13, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 64, 64), dbg-instr-ref(1, 0), debug-location !11
90+
renamable $x0 = LDRXui killed renamable $x0, 0, debug-instr-number 2 :: (load (s64) from %ir.agg.result)
91+
DBG_INSTR_REF !13, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 64, 32), dbg-instr-ref(2, 0), debug-location !11

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