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[RISCV] SPLAT_VECTOR of bf16 should not require Zvfhmin.
The custom lowering converts to f32, splats as f32, then narrows to the vector to bf16. None of that requires Zvfhmin. Add new bf16 test files without Zvfh/Zvfmin in their RUN lines. I will remove the bf16 tests from other files in a follow up patch.
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8 files changed

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-3
lines changed

8 files changed

+973
-3
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1105,7 +1105,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
11051105
if (Subtarget.hasStdExtZfbfmin()) {
11061106
if (Subtarget.hasVInstructionsF16())
11071107
setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
1108-
else if (Subtarget.hasVInstructionsF16Minimal())
1108+
else
11091109
setOperationAction(ISD::SPLAT_VECTOR, VT, Custom);
11101110
}
11111111
setOperationAction({ISD::VP_MERGE, ISD::VP_SELECT, ISD::SELECT}, VT,
@@ -1343,7 +1343,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
13431343
if (Subtarget.hasStdExtZfbfmin()) {
13441344
if (Subtarget.hasVInstructionsF16())
13451345
setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
1346-
else if (Subtarget.hasVInstructionsF16Minimal())
1346+
else
13471347
setOperationAction(ISD::SPLAT_VECTOR, VT, Custom);
13481348
}
13491349
setOperationAction(
@@ -6739,7 +6739,6 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
67396739
!Subtarget.hasVInstructionsF16())) ||
67406740
(Op.getValueType().getScalarType() == MVT::bf16 &&
67416741
(Subtarget.hasVInstructionsBF16() && Subtarget.hasStdExtZfbfmin() &&
6742-
Subtarget.hasVInstructionsF16Minimal() &&
67436742
!Subtarget.hasVInstructionsF16()))) {
67446743
if (Op.getValueType() == MVT::nxv32f16 ||
67456744
Op.getValueType() == MVT::nxv32bf16)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-bf16.ll

Lines changed: 125 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,125 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mtriple=riscv32 -mattr=+d,+v,+experimental-zfbfmin,+experimental-zvfbfmin -target-abi=ilp32d \
3+
; RUN: -verify-machineinstrs < %s | FileCheck %s
4+
; RUN: llc -mtriple=riscv64 -mattr=+d,+v,+experimental-zfbfmin,+experimental-zvfbfmin -target-abi=lp64d \
5+
; RUN: -verify-machineinstrs < %s | FileCheck %s
6+
7+
define <2 x bfloat> @select_v2bf16(i1 zeroext %c, <2 x bfloat> %a, <2 x bfloat> %b) {
8+
; CHECK-LABEL: select_v2bf16:
9+
; CHECK: # %bb.0:
10+
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
11+
; CHECK-NEXT: vmv.v.x v10, a0
12+
; CHECK-NEXT: vmsne.vi v0, v10, 0
13+
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
14+
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
15+
; CHECK-NEXT: ret
16+
%v = select i1 %c, <2 x bfloat> %a, <2 x bfloat> %b
17+
ret <2 x bfloat> %v
18+
}
19+
20+
define <2 x bfloat> @selectcc_v2bf16(bfloat %a, bfloat %b, <2 x bfloat> %c, <2 x bfloat> %d) {
21+
; CHECK-LABEL: selectcc_v2bf16:
22+
; CHECK: # %bb.0:
23+
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
24+
; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
25+
; CHECK-NEXT: feq.s a0, fa4, fa5
26+
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
27+
; CHECK-NEXT: vmv.v.x v10, a0
28+
; CHECK-NEXT: vmsne.vi v0, v10, 0
29+
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
30+
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
31+
; CHECK-NEXT: ret
32+
%cmp = fcmp oeq bfloat %a, %b
33+
%v = select i1 %cmp, <2 x bfloat> %c, <2 x bfloat> %d
34+
ret <2 x bfloat> %v
35+
}
36+
37+
define <4 x bfloat> @select_v4bf16(i1 zeroext %c, <4 x bfloat> %a, <4 x bfloat> %b) {
38+
; CHECK-LABEL: select_v4bf16:
39+
; CHECK: # %bb.0:
40+
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
41+
; CHECK-NEXT: vmv.v.x v10, a0
42+
; CHECK-NEXT: vmsne.vi v0, v10, 0
43+
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
44+
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
45+
; CHECK-NEXT: ret
46+
%v = select i1 %c, <4 x bfloat> %a, <4 x bfloat> %b
47+
ret <4 x bfloat> %v
48+
}
49+
50+
define <4 x bfloat> @selectcc_v4bf16(bfloat %a, bfloat %b, <4 x bfloat> %c, <4 x bfloat> %d) {
51+
; CHECK-LABEL: selectcc_v4bf16:
52+
; CHECK: # %bb.0:
53+
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
54+
; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
55+
; CHECK-NEXT: feq.s a0, fa4, fa5
56+
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
57+
; CHECK-NEXT: vmv.v.x v10, a0
58+
; CHECK-NEXT: vmsne.vi v0, v10, 0
59+
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
60+
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
61+
; CHECK-NEXT: ret
62+
%cmp = fcmp oeq bfloat %a, %b
63+
%v = select i1 %cmp, <4 x bfloat> %c, <4 x bfloat> %d
64+
ret <4 x bfloat> %v
65+
}
66+
67+
define <8 x bfloat> @select_v8bf16(i1 zeroext %c, <8 x bfloat> %a, <8 x bfloat> %b) {
68+
; CHECK-LABEL: select_v8bf16:
69+
; CHECK: # %bb.0:
70+
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
71+
; CHECK-NEXT: vmv.v.x v10, a0
72+
; CHECK-NEXT: vmsne.vi v0, v10, 0
73+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
74+
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
75+
; CHECK-NEXT: ret
76+
%v = select i1 %c, <8 x bfloat> %a, <8 x bfloat> %b
77+
ret <8 x bfloat> %v
78+
}
79+
80+
define <8 x bfloat> @selectcc_v8bf16(bfloat %a, bfloat %b, <8 x bfloat> %c, <8 x bfloat> %d) {
81+
; CHECK-LABEL: selectcc_v8bf16:
82+
; CHECK: # %bb.0:
83+
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
84+
; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
85+
; CHECK-NEXT: feq.s a0, fa4, fa5
86+
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
87+
; CHECK-NEXT: vmv.v.x v10, a0
88+
; CHECK-NEXT: vmsne.vi v0, v10, 0
89+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
90+
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
91+
; CHECK-NEXT: ret
92+
%cmp = fcmp oeq bfloat %a, %b
93+
%v = select i1 %cmp, <8 x bfloat> %c, <8 x bfloat> %d
94+
ret <8 x bfloat> %v
95+
}
96+
97+
define <16 x bfloat> @select_v16bf16(i1 zeroext %c, <16 x bfloat> %a, <16 x bfloat> %b) {
98+
; CHECK-LABEL: select_v16bf16:
99+
; CHECK: # %bb.0:
100+
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
101+
; CHECK-NEXT: vmv.v.x v12, a0
102+
; CHECK-NEXT: vmsne.vi v0, v12, 0
103+
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
104+
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
105+
; CHECK-NEXT: ret
106+
%v = select i1 %c, <16 x bfloat> %a, <16 x bfloat> %b
107+
ret <16 x bfloat> %v
108+
}
109+
110+
define <16 x bfloat> @selectcc_v16bf16(bfloat %a, bfloat %b, <16 x bfloat> %c, <16 x bfloat> %d) {
111+
; CHECK-LABEL: selectcc_v16bf16:
112+
; CHECK: # %bb.0:
113+
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
114+
; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
115+
; CHECK-NEXT: feq.s a0, fa4, fa5
116+
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
117+
; CHECK-NEXT: vmv.v.x v12, a0
118+
; CHECK-NEXT: vmsne.vi v0, v12, 0
119+
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
120+
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
121+
; CHECK-NEXT: ret
122+
%cmp = fcmp oeq bfloat %a, %b
123+
%v = select i1 %cmp, <16 x bfloat> %c, <16 x bfloat> %d
124+
ret <16 x bfloat> %v
125+
}

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge-bf16.ll

Lines changed: 117 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,117 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mtriple=riscv32 -mattr=+d,+v,+m,+experimental-zfbfmin,+experimental-zvfbfmin -target-abi=ilp32d \
3+
; RUN: -verify-machineinstrs < %s | FileCheck %s
4+
; RUN: llc -mtriple=riscv64 -mattr=+d,+v,+m,+experimental-zfbfmin,+experimental-zvfbfmin -target-abi=lp64d \
5+
; RUN: -verify-machineinstrs < %s | FileCheck %s
6+
7+
declare <2 x bfloat> @llvm.vp.merge.v2bf16(<2 x i1>, <2 x bfloat>, <2 x bfloat>, i32)
8+
9+
define <2 x bfloat> @vpmerge_vv_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, <2 x i1> %m, i32 zeroext %evl) {
10+
; CHECK-LABEL: vpmerge_vv_v2bf16:
11+
; CHECK: # %bb.0:
12+
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
13+
; CHECK-NEXT: vmerge.vvm v9, v9, v8, v0
14+
; CHECK-NEXT: vmv1r.v v8, v9
15+
; CHECK-NEXT: ret
16+
%v = call <2 x bfloat> @llvm.vp.merge.v2bf16(<2 x i1> %m, <2 x bfloat> %va, <2 x bfloat> %vb, i32 %evl)
17+
ret <2 x bfloat> %v
18+
}
19+
20+
define <2 x bfloat> @vpmerge_vf_v2bf16(bfloat %a, <2 x bfloat> %vb, <2 x i1> %m, i32 zeroext %evl) {
21+
; CHECK-LABEL: vpmerge_vf_v2bf16:
22+
; CHECK: # %bb.0:
23+
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
24+
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
25+
; CHECK-NEXT: vfmv.v.f v9, fa5
26+
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
27+
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
28+
; CHECK-NEXT: ret
29+
%elt.head = insertelement <2 x bfloat> poison, bfloat %a, i32 0
30+
%va = shufflevector <2 x bfloat> %elt.head, <2 x bfloat> poison, <2 x i32> zeroinitializer
31+
%v = call <2 x bfloat> @llvm.vp.merge.v2bf16(<2 x i1> %m, <2 x bfloat> %va, <2 x bfloat> %vb, i32 %evl)
32+
ret <2 x bfloat> %v
33+
}
34+
35+
declare <4 x bfloat> @llvm.vp.merge.v4bf16(<4 x i1>, <4 x bfloat>, <4 x bfloat>, i32)
36+
37+
define <4 x bfloat> @vpmerge_vv_v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, <4 x i1> %m, i32 zeroext %evl) {
38+
; CHECK-LABEL: vpmerge_vv_v4bf16:
39+
; CHECK: # %bb.0:
40+
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
41+
; CHECK-NEXT: vmerge.vvm v9, v9, v8, v0
42+
; CHECK-NEXT: vmv1r.v v8, v9
43+
; CHECK-NEXT: ret
44+
%v = call <4 x bfloat> @llvm.vp.merge.v4bf16(<4 x i1> %m, <4 x bfloat> %va, <4 x bfloat> %vb, i32 %evl)
45+
ret <4 x bfloat> %v
46+
}
47+
48+
define <4 x bfloat> @vpmerge_vf_v4bf16(bfloat %a, <4 x bfloat> %vb, <4 x i1> %m, i32 zeroext %evl) {
49+
; CHECK-LABEL: vpmerge_vf_v4bf16:
50+
; CHECK: # %bb.0:
51+
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
52+
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
53+
; CHECK-NEXT: vfmv.v.f v9, fa5
54+
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
55+
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
56+
; CHECK-NEXT: ret
57+
%elt.head = insertelement <4 x bfloat> poison, bfloat %a, i32 0
58+
%va = shufflevector <4 x bfloat> %elt.head, <4 x bfloat> poison, <4 x i32> zeroinitializer
59+
%v = call <4 x bfloat> @llvm.vp.merge.v4bf16(<4 x i1> %m, <4 x bfloat> %va, <4 x bfloat> %vb, i32 %evl)
60+
ret <4 x bfloat> %v
61+
}
62+
63+
declare <8 x bfloat> @llvm.vp.merge.v8bf16(<8 x i1>, <8 x bfloat>, <8 x bfloat>, i32)
64+
65+
define <8 x bfloat> @vpmerge_vv_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, <8 x i1> %m, i32 zeroext %evl) {
66+
; CHECK-LABEL: vpmerge_vv_v8bf16:
67+
; CHECK: # %bb.0:
68+
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
69+
; CHECK-NEXT: vmerge.vvm v9, v9, v8, v0
70+
; CHECK-NEXT: vmv1r.v v8, v9
71+
; CHECK-NEXT: ret
72+
%v = call <8 x bfloat> @llvm.vp.merge.v8bf16(<8 x i1> %m, <8 x bfloat> %va, <8 x bfloat> %vb, i32 %evl)
73+
ret <8 x bfloat> %v
74+
}
75+
76+
define <8 x bfloat> @vpmerge_vf_v8bf16(bfloat %a, <8 x bfloat> %vb, <8 x i1> %m, i32 zeroext %evl) {
77+
; CHECK-LABEL: vpmerge_vf_v8bf16:
78+
; CHECK: # %bb.0:
79+
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
80+
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
81+
; CHECK-NEXT: vfmv.v.f v10, fa5
82+
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
83+
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
84+
; CHECK-NEXT: ret
85+
%elt.head = insertelement <8 x bfloat> poison, bfloat %a, i32 0
86+
%va = shufflevector <8 x bfloat> %elt.head, <8 x bfloat> poison, <8 x i32> zeroinitializer
87+
%v = call <8 x bfloat> @llvm.vp.merge.v8bf16(<8 x i1> %m, <8 x bfloat> %va, <8 x bfloat> %vb, i32 %evl)
88+
ret <8 x bfloat> %v
89+
}
90+
91+
declare <16 x bfloat> @llvm.vp.merge.v16bf16(<16 x i1>, <16 x bfloat>, <16 x bfloat>, i32)
92+
93+
define <16 x bfloat> @vpmerge_vv_v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, <16 x i1> %m, i32 zeroext %evl) {
94+
; CHECK-LABEL: vpmerge_vv_v16bf16:
95+
; CHECK: # %bb.0:
96+
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
97+
; CHECK-NEXT: vmerge.vvm v10, v10, v8, v0
98+
; CHECK-NEXT: vmv2r.v v8, v10
99+
; CHECK-NEXT: ret
100+
%v = call <16 x bfloat> @llvm.vp.merge.v16bf16(<16 x i1> %m, <16 x bfloat> %va, <16 x bfloat> %vb, i32 %evl)
101+
ret <16 x bfloat> %v
102+
}
103+
104+
define <16 x bfloat> @vpmerge_vf_v16bf16(bfloat %a, <16 x bfloat> %vb, <16 x i1> %m, i32 zeroext %evl) {
105+
; CHECK-LABEL: vpmerge_vf_v16bf16:
106+
; CHECK: # %bb.0:
107+
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
108+
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
109+
; CHECK-NEXT: vfmv.v.f v12, fa5
110+
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
111+
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t
112+
; CHECK-NEXT: ret
113+
%elt.head = insertelement <16 x bfloat> poison, bfloat %a, i32 0
114+
%va = shufflevector <16 x bfloat> %elt.head, <16 x bfloat> poison, <16 x i32> zeroinitializer
115+
%v = call <16 x bfloat> @llvm.vp.merge.v16bf16(<16 x i1> %m, <16 x bfloat> %va, <16 x bfloat> %vb, i32 %evl)
116+
ret <16 x bfloat> %v
117+
}

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp-bf16.ll

Lines changed: 53 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,53 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mtriple=riscv32 -mattr=+d,+v,+m,+experimental-zfbfmin,+experimental-zvfbfmin -target-abi=ilp32d \
3+
; RUN: -verify-machineinstrs < %s | FileCheck %s
4+
; RUN: llc -mtriple=riscv64 -mattr=+d,+v,+m,+experimental-zfbfmin,+experimental-zvfbfmin -target-abi=lp64d \
5+
; RUN: -verify-machineinstrs < %s | FileCheck %s
6+
7+
declare <2 x bfloat> @llvm.vp.select.v2bf16(<2 x i1>, <2 x bfloat>, <2 x bfloat>, i32)
8+
9+
define <2 x bfloat> @select_v2bf16(<2 x i1> %a, <2 x bfloat> %b, <2 x bfloat> %c, i32 zeroext %evl) {
10+
; CHECK-LABEL: select_v2bf16:
11+
; CHECK: # %bb.0:
12+
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
13+
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
14+
; CHECK-NEXT: ret
15+
%v = call <2 x bfloat> @llvm.vp.select.v2bf16(<2 x i1> %a, <2 x bfloat> %b, <2 x bfloat> %c, i32 %evl)
16+
ret <2 x bfloat> %v
17+
}
18+
19+
declare <4 x bfloat> @llvm.vp.select.v4bf16(<4 x i1>, <4 x bfloat>, <4 x bfloat>, i32)
20+
21+
define <4 x bfloat> @select_v4bf16(<4 x i1> %a, <4 x bfloat> %b, <4 x bfloat> %c, i32 zeroext %evl) {
22+
; CHECK-LABEL: select_v4bf16:
23+
; CHECK: # %bb.0:
24+
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
25+
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
26+
; CHECK-NEXT: ret
27+
%v = call <4 x bfloat> @llvm.vp.select.v4bf16(<4 x i1> %a, <4 x bfloat> %b, <4 x bfloat> %c, i32 %evl)
28+
ret <4 x bfloat> %v
29+
}
30+
31+
declare <8 x bfloat> @llvm.vp.select.v8bf16(<8 x i1>, <8 x bfloat>, <8 x bfloat>, i32)
32+
33+
define <8 x bfloat> @select_v8bf16(<8 x i1> %a, <8 x bfloat> %b, <8 x bfloat> %c, i32 zeroext %evl) {
34+
; CHECK-LABEL: select_v8bf16:
35+
; CHECK: # %bb.0:
36+
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
37+
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
38+
; CHECK-NEXT: ret
39+
%v = call <8 x bfloat> @llvm.vp.select.v8bf16(<8 x i1> %a, <8 x bfloat> %b, <8 x bfloat> %c, i32 %evl)
40+
ret <8 x bfloat> %v
41+
}
42+
43+
declare <16 x bfloat> @llvm.vp.select.v16bf16(<16 x i1>, <16 x bfloat>, <16 x bfloat>, i32)
44+
45+
define <16 x bfloat> @select_v16bf16(<16 x i1> %a, <16 x bfloat> %b, <16 x bfloat> %c, i32 zeroext %evl) {
46+
; CHECK-LABEL: select_v16bf16:
47+
; CHECK: # %bb.0:
48+
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
49+
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
50+
; CHECK-NEXT: ret
51+
%v = call <16 x bfloat> @llvm.vp.select.v16bf16(<16 x i1> %a, <16 x bfloat> %b, <16 x bfloat> %c, i32 %evl)
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ret <16 x bfloat> %v
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}

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