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[RISCV][test] Add VANDN tests with constants
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‎llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll

Lines changed: 178 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,10 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
22
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32
33
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64
4-
; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB32
5-
; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB64
4+
; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB-NOZBB,CHECK-ZVKB32
5+
; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB-NOZBB,CHECK-ZVKB64
6+
; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb,+zbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB-ZBB,CHECK-ZVKB32
7+
; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb,+zbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB-ZBB,CHECK-ZVKB64
68

79
define <vscale x 1 x i8> @vandn_vv_nxv1i8(<vscale x 1 x i8> %x, <vscale x 1 x i8> %y) {
810
; CHECK-LABEL: vandn_vv_nxv1i8:
@@ -1931,3 +1933,177 @@ define <vscale x 8 x i64> @vandn_vx_swapped_nxv8i64(i64 %x, <vscale x 8 x i64> %
19311933
%b = and <vscale x 8 x i64> %splat, %y
19321934
ret <vscale x 8 x i64> %b
19331935
}
1936+
1937+
define <vscale x 1 x i16> @vandn_vx_imm16(<vscale x 1 x i16> %x) {
1938+
; CHECK-LABEL: vandn_vx_imm16:
1939+
; CHECK: # %bb.0:
1940+
; CHECK-NEXT: lui a0, 8
1941+
; CHECK-NEXT: addi a0, a0, -1
1942+
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
1943+
; CHECK-NEXT: vand.vx v8, v8, a0
1944+
; CHECK-NEXT: ret
1945+
;
1946+
; CHECK-ZVKB-LABEL: vandn_vx_imm16:
1947+
; CHECK-ZVKB: # %bb.0:
1948+
; CHECK-ZVKB-NEXT: lui a0, 8
1949+
; CHECK-ZVKB-NEXT: addi a0, a0, -1
1950+
; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
1951+
; CHECK-ZVKB-NEXT: vand.vx v8, v8, a0
1952+
; CHECK-ZVKB-NEXT: ret
1953+
%a = and <vscale x 1 x i16> splat (i16 32767), %x
1954+
ret <vscale x 1 x i16> %a
1955+
}
1956+
1957+
define <vscale x 1 x i16> @vandn_vx_swapped_imm16(<vscale x 1 x i16> %x) {
1958+
; CHECK-LABEL: vandn_vx_swapped_imm16:
1959+
; CHECK: # %bb.0:
1960+
; CHECK-NEXT: lui a0, 8
1961+
; CHECK-NEXT: addi a0, a0, -1
1962+
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
1963+
; CHECK-NEXT: vand.vx v8, v8, a0
1964+
; CHECK-NEXT: ret
1965+
;
1966+
; CHECK-ZVKB-LABEL: vandn_vx_swapped_imm16:
1967+
; CHECK-ZVKB: # %bb.0:
1968+
; CHECK-ZVKB-NEXT: lui a0, 8
1969+
; CHECK-ZVKB-NEXT: addi a0, a0, -1
1970+
; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
1971+
; CHECK-ZVKB-NEXT: vand.vx v8, v8, a0
1972+
; CHECK-ZVKB-NEXT: ret
1973+
%a = and <vscale x 1 x i16> %x, splat (i16 32767)
1974+
ret <vscale x 1 x i16> %a
1975+
}
1976+
1977+
define <vscale x 1 x i64> @vandn_vx_imm64(<vscale x 1 x i64> %x) {
1978+
; CHECK-RV32-LABEL: vandn_vx_imm64:
1979+
; CHECK-RV32: # %bb.0:
1980+
; CHECK-RV32-NEXT: addi sp, sp, -16
1981+
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
1982+
; CHECK-RV32-NEXT: lui a0, 1044480
1983+
; CHECK-RV32-NEXT: li a1, 255
1984+
; CHECK-RV32-NEXT: sw a1, 8(sp)
1985+
; CHECK-RV32-NEXT: sw a0, 12(sp)
1986+
; CHECK-RV32-NEXT: addi a0, sp, 8
1987+
; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma
1988+
; CHECK-RV32-NEXT: vlse64.v v9, (a0), zero
1989+
; CHECK-RV32-NEXT: vand.vv v8, v8, v9
1990+
; CHECK-RV32-NEXT: addi sp, sp, 16
1991+
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 0
1992+
; CHECK-RV32-NEXT: ret
1993+
;
1994+
; CHECK-RV64-LABEL: vandn_vx_imm64:
1995+
; CHECK-RV64: # %bb.0:
1996+
; CHECK-RV64-NEXT: li a0, -1
1997+
; CHECK-RV64-NEXT: slli a0, a0, 56
1998+
; CHECK-RV64-NEXT: addi a0, a0, 255
1999+
; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma
2000+
; CHECK-RV64-NEXT: vand.vx v8, v8, a0
2001+
; CHECK-RV64-NEXT: ret
2002+
;
2003+
; CHECK-ZVKB32-LABEL: vandn_vx_imm64:
2004+
; CHECK-ZVKB32: # %bb.0:
2005+
; CHECK-ZVKB32-NEXT: addi sp, sp, -16
2006+
; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 16
2007+
; CHECK-ZVKB32-NEXT: lui a0, 1044480
2008+
; CHECK-ZVKB32-NEXT: li a1, 255
2009+
; CHECK-ZVKB32-NEXT: sw a1, 8(sp)
2010+
; CHECK-ZVKB32-NEXT: sw a0, 12(sp)
2011+
; CHECK-ZVKB32-NEXT: addi a0, sp, 8
2012+
; CHECK-ZVKB32-NEXT: vsetvli a1, zero, e64, m1, ta, ma
2013+
; CHECK-ZVKB32-NEXT: vlse64.v v9, (a0), zero
2014+
; CHECK-ZVKB32-NEXT: vand.vv v8, v8, v9
2015+
; CHECK-ZVKB32-NEXT: addi sp, sp, 16
2016+
; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 0
2017+
; CHECK-ZVKB32-NEXT: ret
2018+
;
2019+
; CHECK-ZVKB64-LABEL: vandn_vx_imm64:
2020+
; CHECK-ZVKB64: # %bb.0:
2021+
; CHECK-ZVKB64-NEXT: li a0, -1
2022+
; CHECK-ZVKB64-NEXT: slli a0, a0, 56
2023+
; CHECK-ZVKB64-NEXT: addi a0, a0, 255
2024+
; CHECK-ZVKB64-NEXT: vsetvli a1, zero, e64, m1, ta, ma
2025+
; CHECK-ZVKB64-NEXT: vand.vx v8, v8, a0
2026+
; CHECK-ZVKB64-NEXT: ret
2027+
%a = and <vscale x 1 x i64> %x, splat (i64 -72057594037927681)
2028+
ret <vscale x 1 x i64> %a
2029+
}
2030+
2031+
define <vscale x 1 x i16> @vandn_vx_multi_imm16(<vscale x 1 x i16> %x, <vscale x 1 x i16> %y) {
2032+
; CHECK-LABEL: vandn_vx_multi_imm16:
2033+
; CHECK: # %bb.0:
2034+
; CHECK-NEXT: lui a0, 4
2035+
; CHECK-NEXT: addi a0, a0, -1
2036+
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
2037+
; CHECK-NEXT: vand.vx v8, v8, a0
2038+
; CHECK-NEXT: vand.vx v9, v9, a0
2039+
; CHECK-NEXT: vadd.vv v8, v8, v9
2040+
; CHECK-NEXT: ret
2041+
;
2042+
; CHECK-ZVKB-LABEL: vandn_vx_multi_imm16:
2043+
; CHECK-ZVKB: # %bb.0:
2044+
; CHECK-ZVKB-NEXT: lui a0, 4
2045+
; CHECK-ZVKB-NEXT: addi a0, a0, -1
2046+
; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
2047+
; CHECK-ZVKB-NEXT: vand.vx v8, v8, a0
2048+
; CHECK-ZVKB-NEXT: vand.vx v9, v9, a0
2049+
; CHECK-ZVKB-NEXT: vadd.vv v8, v8, v9
2050+
; CHECK-ZVKB-NEXT: ret
2051+
%a = and <vscale x 1 x i16> %x, splat (i16 16383)
2052+
%b = and <vscale x 1 x i16> %y, splat (i16 16383)
2053+
%c = add <vscale x 1 x i16> %a, %b
2054+
ret <vscale x 1 x i16> %c
2055+
}
2056+
2057+
define <vscale x 1 x i16> @vandn_vx_multi_scalar_imm16(<vscale x 1 x i16> %x, i16 %y) {
2058+
; CHECK-LABEL: vandn_vx_multi_scalar_imm16:
2059+
; CHECK: # %bb.0:
2060+
; CHECK-NEXT: lui a1, 8
2061+
; CHECK-NEXT: addi a1, a1, -1
2062+
; CHECK-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
2063+
; CHECK-NEXT: vand.vx v8, v8, a1
2064+
; CHECK-NEXT: or a0, a0, a1
2065+
; CHECK-NEXT: vadd.vx v8, v8, a0
2066+
; CHECK-NEXT: ret
2067+
;
2068+
; CHECK-ZVKB-LABEL: vandn_vx_multi_scalar_imm16:
2069+
; CHECK-ZVKB: # %bb.0:
2070+
; CHECK-ZVKB-NEXT: lui a1, 8
2071+
; CHECK-ZVKB-NEXT: addi a1, a1, -1
2072+
; CHECK-ZVKB-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
2073+
; CHECK-ZVKB-NEXT: vand.vx v8, v8, a1
2074+
; CHECK-ZVKB-NEXT: or a0, a0, a1
2075+
; CHECK-ZVKB-NEXT: vadd.vx v8, v8, a0
2076+
; CHECK-ZVKB-NEXT: ret
2077+
%a = and <vscale x 1 x i16> %x, splat (i16 32767)
2078+
%b = or i16 %y, 32767
2079+
%head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
2080+
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
2081+
%c = add <vscale x 1 x i16> %a, %splat
2082+
ret <vscale x 1 x i16> %c
2083+
}
2084+
2085+
define <vscale x 1 x i16> @vand_vadd_vx_imm16(<vscale x 1 x i16> %x) {
2086+
; CHECK-LABEL: vand_vadd_vx_imm16:
2087+
; CHECK: # %bb.0:
2088+
; CHECK-NEXT: lui a0, 8
2089+
; CHECK-NEXT: addi a0, a0, -1
2090+
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
2091+
; CHECK-NEXT: vand.vx v8, v8, a0
2092+
; CHECK-NEXT: vadd.vx v8, v8, a0
2093+
; CHECK-NEXT: ret
2094+
;
2095+
; CHECK-ZVKB-LABEL: vand_vadd_vx_imm16:
2096+
; CHECK-ZVKB: # %bb.0:
2097+
; CHECK-ZVKB-NEXT: lui a0, 8
2098+
; CHECK-ZVKB-NEXT: addi a0, a0, -1
2099+
; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
2100+
; CHECK-ZVKB-NEXT: vand.vx v8, v8, a0
2101+
; CHECK-ZVKB-NEXT: vadd.vx v8, v8, a0
2102+
; CHECK-ZVKB-NEXT: ret
2103+
%a = and <vscale x 1 x i16> %x, splat (i16 32767)
2104+
%b = add <vscale x 1 x i16> %a, splat (i16 32767)
2105+
ret <vscale x 1 x i16> %b
2106+
}
2107+
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
2108+
; CHECK-ZVKB-NOZBB: {{.*}}
2109+
; CHECK-ZVKB-ZBB: {{.*}}

‎llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll

Lines changed: 117 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1429,3 +1429,120 @@ define <vscale x 8 x i64> @vandn_vx_vp_nxv8i64(i64 %a, <vscale x 8 x i64> %b, <v
14291429
%x = call <vscale x 8 x i64> @llvm.vp.and.nxv8i64(<vscale x 8 x i64> %b, <vscale x 8 x i64> %splat.not.a, <vscale x 8 x i1> %mask, i32 %evl)
14301430
ret <vscale x 8 x i64> %x
14311431
}
1432+
1433+
define <vscale x 1 x i16> @vandn_vx_vp_imm16(<vscale x 1 x i16> %x, <vscale x 1 x i1> %mask, i32 zeroext %evl) {
1434+
; CHECK-LABEL: vandn_vx_vp_imm16:
1435+
; CHECK: # %bb.0:
1436+
; CHECK-NEXT: lui a1, 8
1437+
; CHECK-NEXT: addi a1, a1, -1
1438+
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
1439+
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
1440+
; CHECK-NEXT: ret
1441+
;
1442+
; CHECK-ZVKB-LABEL: vandn_vx_vp_imm16:
1443+
; CHECK-ZVKB: # %bb.0:
1444+
; CHECK-ZVKB-NEXT: lui a1, 8
1445+
; CHECK-ZVKB-NEXT: addi a1, a1, -1
1446+
; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
1447+
; CHECK-ZVKB-NEXT: vand.vx v8, v8, a1, v0.t
1448+
; CHECK-ZVKB-NEXT: ret
1449+
%a = call <vscale x 1 x i16> @llvm.vp.and.nxv1i16(<vscale x 1 x i16> splat (i16 32767), <vscale x 1 x i16> %x, <vscale x 1 x i1> %mask, i32 %evl)
1450+
ret <vscale x 1 x i16> %a
1451+
}
1452+
1453+
define <vscale x 1 x i16> @vandn_vx_vp_swapped_imm16(<vscale x 1 x i16> %x, <vscale x 1 x i1> %mask, i32 zeroext %evl) {
1454+
; CHECK-LABEL: vandn_vx_vp_swapped_imm16:
1455+
; CHECK: # %bb.0:
1456+
; CHECK-NEXT: lui a1, 8
1457+
; CHECK-NEXT: addi a1, a1, -1
1458+
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
1459+
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
1460+
; CHECK-NEXT: ret
1461+
;
1462+
; CHECK-ZVKB-LABEL: vandn_vx_vp_swapped_imm16:
1463+
; CHECK-ZVKB: # %bb.0:
1464+
; CHECK-ZVKB-NEXT: lui a1, 8
1465+
; CHECK-ZVKB-NEXT: addi a1, a1, -1
1466+
; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
1467+
; CHECK-ZVKB-NEXT: vand.vx v8, v8, a1, v0.t
1468+
; CHECK-ZVKB-NEXT: ret
1469+
%a = call <vscale x 1 x i16> @llvm.vp.and.nxv1i16(<vscale x 1 x i16> %x, <vscale x 1 x i16> splat (i16 32767), <vscale x 1 x i1> %mask, i32 %evl)
1470+
ret <vscale x 1 x i16> %a
1471+
}
1472+
1473+
define <vscale x 1 x i64> @vandn_vx_vp_imm64(<vscale x 1 x i64> %x, <vscale x 1 x i1> %mask, i32 zeroext %evl) {
1474+
; CHECK-RV32-LABEL: vandn_vx_vp_imm64:
1475+
; CHECK-RV32: # %bb.0:
1476+
; CHECK-RV32-NEXT: addi sp, sp, -16
1477+
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
1478+
; CHECK-RV32-NEXT: lui a1, 1044480
1479+
; CHECK-RV32-NEXT: li a2, 255
1480+
; CHECK-RV32-NEXT: sw a2, 8(sp)
1481+
; CHECK-RV32-NEXT: sw a1, 12(sp)
1482+
; CHECK-RV32-NEXT: addi a1, sp, 8
1483+
; CHECK-RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
1484+
; CHECK-RV32-NEXT: vlse64.v v9, (a1), zero
1485+
; CHECK-RV32-NEXT: vand.vv v8, v8, v9, v0.t
1486+
; CHECK-RV32-NEXT: addi sp, sp, 16
1487+
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 0
1488+
; CHECK-RV32-NEXT: ret
1489+
;
1490+
; CHECK-RV64-LABEL: vandn_vx_vp_imm64:
1491+
; CHECK-RV64: # %bb.0:
1492+
; CHECK-RV64-NEXT: li a1, -1
1493+
; CHECK-RV64-NEXT: slli a1, a1, 56
1494+
; CHECK-RV64-NEXT: addi a1, a1, 255
1495+
; CHECK-RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
1496+
; CHECK-RV64-NEXT: vand.vx v8, v8, a1, v0.t
1497+
; CHECK-RV64-NEXT: ret
1498+
;
1499+
; CHECK-ZVKB32-LABEL: vandn_vx_vp_imm64:
1500+
; CHECK-ZVKB32: # %bb.0:
1501+
; CHECK-ZVKB32-NEXT: addi sp, sp, -16
1502+
; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 16
1503+
; CHECK-ZVKB32-NEXT: lui a1, 1044480
1504+
; CHECK-ZVKB32-NEXT: li a2, 255
1505+
; CHECK-ZVKB32-NEXT: sw a2, 8(sp)
1506+
; CHECK-ZVKB32-NEXT: sw a1, 12(sp)
1507+
; CHECK-ZVKB32-NEXT: addi a1, sp, 8
1508+
; CHECK-ZVKB32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
1509+
; CHECK-ZVKB32-NEXT: vlse64.v v9, (a1), zero
1510+
; CHECK-ZVKB32-NEXT: vand.vv v8, v8, v9, v0.t
1511+
; CHECK-ZVKB32-NEXT: addi sp, sp, 16
1512+
; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 0
1513+
; CHECK-ZVKB32-NEXT: ret
1514+
;
1515+
; CHECK-ZVKB64-LABEL: vandn_vx_vp_imm64:
1516+
; CHECK-ZVKB64: # %bb.0:
1517+
; CHECK-ZVKB64-NEXT: li a1, -1
1518+
; CHECK-ZVKB64-NEXT: slli a1, a1, 56
1519+
; CHECK-ZVKB64-NEXT: addi a1, a1, 255
1520+
; CHECK-ZVKB64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
1521+
; CHECK-ZVKB64-NEXT: vand.vx v8, v8, a1, v0.t
1522+
; CHECK-ZVKB64-NEXT: ret
1523+
%a = call <vscale x 1 x i64> @llvm.vp.and.nxv1i64(<vscale x 1 x i64> %x, <vscale x 1 x i64> splat (i64 -72057594037927681), <vscale x 1 x i1> %mask, i32 %evl)
1524+
ret <vscale x 1 x i64> %a
1525+
}
1526+
1527+
define <vscale x 1 x i16> @vand_vadd_vx_vp_imm16(<vscale x 1 x i16> %x, <vscale x 1 x i1> %mask, i32 zeroext %evl) {
1528+
; CHECK-LABEL: vand_vadd_vx_vp_imm16:
1529+
; CHECK: # %bb.0:
1530+
; CHECK-NEXT: lui a1, 8
1531+
; CHECK-NEXT: addi a1, a1, -1
1532+
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
1533+
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
1534+
; CHECK-NEXT: vadd.vx v8, v8, a1, v0.t
1535+
; CHECK-NEXT: ret
1536+
;
1537+
; CHECK-ZVKB-LABEL: vand_vadd_vx_vp_imm16:
1538+
; CHECK-ZVKB: # %bb.0:
1539+
; CHECK-ZVKB-NEXT: lui a1, 8
1540+
; CHECK-ZVKB-NEXT: addi a1, a1, -1
1541+
; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
1542+
; CHECK-ZVKB-NEXT: vand.vx v8, v8, a1, v0.t
1543+
; CHECK-ZVKB-NEXT: vadd.vx v8, v8, a1, v0.t
1544+
; CHECK-ZVKB-NEXT: ret
1545+
%a = call <vscale x 1 x i16> @llvm.vp.and.nxv1i16(<vscale x 1 x i16> splat (i16 32767), <vscale x 1 x i16> %x, <vscale x 1 x i1> %mask, i32 %evl)
1546+
%b = call <vscale x 1 x i16> @llvm.vp.add.nxv1i16(<vscale x 1 x i16> splat (i16 32767), <vscale x 1 x i16> %a, <vscale x 1 x i1> %mask, i32 %evl)
1547+
ret <vscale x 1 x i16> %b
1548+
}

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