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[RISCV][MC] Support Base P non-GPR pair instructions (#137927)
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9 files changed

+366
-32
lines changed

9 files changed

+366
-32
lines changed

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -807,6 +807,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
807807

808808
bool isSImm5() const { return isSImm<5>(); }
809809
bool isSImm6() const { return isSImm<6>(); }
810+
bool isSImm10() const { return isSImm<10>(); }
810811
bool isSImm11() const { return isSImm<11>(); }
811812
bool isSImm16() const { return isSImm<16>(); }
812813
bool isSImm26() const { return isSImm<26>(); }
@@ -901,6 +902,8 @@ struct RISCVOperand final : public MCParsedAsmOperand {
901902
VK == RISCV::S_QC_ABS20;
902903
}
903904

905+
bool isSImm10Unsigned() const { return isSImm<10>() || isUImm<10>(); }
906+
904907
bool isUImm20LUI() const {
905908
if (!isImm())
906909
return false;
@@ -1532,6 +1535,12 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
15321535
return generateImmOutOfRangeError(
15331536
Operands, ErrorInfo, 0, (1 << 9) - 8,
15341537
"immediate must be a multiple of 8 bytes in the range");
1538+
case Match_InvalidSImm10:
1539+
return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 9),
1540+
(1 << 9) - 1);
1541+
case Match_InvalidSImm10Unsigned:
1542+
return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 9),
1543+
(1 << 10) - 1);
15351544
case Match_InvalidUImm10Lsb00NonZero:
15361545
return generateImmOutOfRangeError(
15371546
Operands, ErrorInfo, 4, (1 << 10) - 4,

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -337,6 +337,8 @@ enum OperandType : unsigned {
337337
OPERAND_SIMM5_PLUS1,
338338
OPERAND_SIMM6,
339339
OPERAND_SIMM6_NONZERO,
340+
OPERAND_SIMM10,
341+
OPERAND_SIMM10_UNSIGNED,
340342
OPERAND_SIMM10_LSB0000_NONZERO,
341343
OPERAND_SIMM11,
342344
OPERAND_SIMM12,

llvm/lib/Target/RISCV/RISCVInstrInfo.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2273,6 +2273,9 @@ include "RISCVInstrInfoV.td"
22732273
include "RISCVInstrInfoZvk.td"
22742274
include "RISCVInstrInfoZvqdotq.td"
22752275

2276+
// Packed SIMD
2277+
include "RISCVInstrInfoP.td"
2278+
22762279
// Compressed
22772280
include "RISCVInstrInfoC.td"
22782281
include "RISCVInstrInfoZc.td"
Lines changed: 163 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,163 @@
1+
//===-- RISCVInstrInfoP.td - RISC-V 'P' instructions -------*- tablegen -*-===//
2+
//
3+
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
// See https://llvm.org/LICENSE.txt for license information.
5+
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
//
7+
//===----------------------------------------------------------------------===//
8+
//
9+
// This file describes the RISC-V instructions from the standard 'Base P'
10+
// Packed SIMD instruction set extension.
11+
//
12+
// This version is still experimental as the 'P' extension hasn't been
13+
// ratified yet.
14+
//
15+
//===----------------------------------------------------------------------===//
16+
17+
//===----------------------------------------------------------------------===//
18+
// Operand and SDNode transformation definitions.
19+
//===----------------------------------------------------------------------===//
20+
21+
def simm10 : RISCVSImmLeafOp<10>;
22+
23+
// A 10-bit signed immediate allowing range [-512, 1023]
24+
// but will decode to [-512, 511].
25+
def simm10_unsigned : RISCVOp {
26+
let ParserMatchClass = SImmAsmOperand<10, "Unsigned">;
27+
let EncoderMethod = "getImmOpValue";
28+
let DecoderMethod = "decodeSImmOperand<10>";
29+
let OperandType = "OPERAND_SIMM10_UNSIGNED";
30+
let MCOperandPredicate = [{
31+
int64_t Imm;
32+
if (!MCOp.evaluateAsConstantImm(Imm))
33+
return false;
34+
return isInt<10>(Imm) || isUInt<10>(Imm);
35+
}];
36+
}
37+
38+
//===----------------------------------------------------------------------===//
39+
// Instruction class templates
40+
//===----------------------------------------------------------------------===//
41+
42+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
43+
class RVPUnaryImm10<bits<7> funct7, string opcodestr,
44+
DAGOperand TyImm10 = simm10>
45+
: RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), (ins TyImm10:$imm10),
46+
opcodestr, "$rd, $imm10"> {
47+
bits<10> imm10;
48+
49+
let Inst{31-25} = funct7;
50+
let Inst{24-16} = imm10{8-0};
51+
let Inst{15} = imm10{9};
52+
}
53+
54+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
55+
class RVPUnaryImm8<bits<8> funct8, string opcodestr>
56+
: RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), (ins uimm8:$uimm8),
57+
opcodestr, "$rd, $uimm8"> {
58+
bits<8> uimm8;
59+
60+
let Inst{31-24} = funct8;
61+
let Inst{23-16} = uimm8;
62+
let Inst{15} = 0b0;
63+
}
64+
65+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
66+
class RVPUnary<bits<3> f, string opcodestr, dag operands, string argstr>
67+
: RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), operands, opcodestr, argstr> {
68+
bits<5> imm;
69+
bits<5> rs1;
70+
71+
let Inst{31} = 0b1;
72+
let Inst{30-28} = f;
73+
let Inst{27} = 0b0;
74+
let Inst{19-15} = rs1;
75+
}
76+
77+
class RVPUnaryImm5<bits<3> f, string opcodestr>
78+
: RVPUnary<f, opcodestr, (ins GPR:$rs1, uimm5:$uimm5), "$rd, $rs1, $uimm5"> {
79+
bits<5> uimm5;
80+
81+
let imm = uimm5;
82+
let Inst{26-25} = 0b01;
83+
let Inst{24-20} = uimm5;
84+
}
85+
86+
class RVPUnaryImm4<bits<3> f, string opcodestr>
87+
: RVPUnary<f, opcodestr, (ins GPR:$rs1, uimm4:$uimm4), "$rd, $rs1, $uimm4"> {
88+
bits<4> uimm4;
89+
90+
let Inst{26-24} = 0b001;
91+
let Inst{23-20} = uimm4;
92+
}
93+
94+
class RVPUnaryImm3<bits<3> f, string opcodestr>
95+
: RVPUnary<f, opcodestr, (ins GPR:$rs1, uimm3:$uimm3), "$rd, $rs1, $uimm3"> {
96+
bits<3> uimm3;
97+
98+
let Inst{26-23} = 0b0001;
99+
let Inst{22-20} = uimm3;
100+
}
101+
102+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
103+
class RVPUnaryWUF<bits<2> w, bits<5> uf, string opcodestr>
104+
: RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), (ins GPR:$rs1),
105+
opcodestr, "$rd, $rs1"> {
106+
let Inst{31-27} = 0b11100;
107+
let Inst{26-25} = w;
108+
let Inst{24-20} = uf;
109+
}
110+
111+
//===----------------------------------------------------------------------===//
112+
// Instructions
113+
//===----------------------------------------------------------------------===//
114+
115+
let Predicates = [HasStdExtP] in {
116+
def CLS : Unary_r<0b011000000011, 0b001, "cls">;
117+
def ABS : Unary_r<0b011000000111, 0b001, "abs">;
118+
} // Predicates = [HasStdExtP]
119+
let Predicates = [HasStdExtP, IsRV32] in
120+
def REV_RV32 : Unary_r<0b011010011111, 0b101, "rev">;
121+
122+
let Predicates = [HasStdExtP, IsRV64] in {
123+
def REV16 : Unary_r<0b011010110000, 0b101, "rev16">;
124+
def REV_RV64 : Unary_r<0b011010111111, 0b101, "rev">;
125+
126+
def CLSW : UnaryW_r<0b011000000011, 0b001, "clsw">;
127+
def ABSW : UnaryW_r<0b011000000111, 0b001, "absw">;
128+
} // Predicates = [HasStdExtP, IsRV64]
129+
130+
let Predicates = [HasStdExtP] in {
131+
def PSLLI_B : RVPUnaryImm3<0b000, "pslli.b">;
132+
def PSLLI_H : RVPUnaryImm4<0b000, "pslli.h">;
133+
def PSSLAI_H : RVPUnaryImm4<0b101, "psslai.h">;
134+
} // Predicates = [HasStdExtP]
135+
let DecoderNamespace = "RV32Only",
136+
Predicates = [HasStdExtP, IsRV32] in
137+
def SSLAI : RVPUnaryImm5<0b101, "sslai">;
138+
let Predicates = [HasStdExtP, IsRV64] in {
139+
def PSLLI_W : RVPUnaryImm5<0b000, "pslli.w">;
140+
def PSSLAI_W : RVPUnaryImm5<0b101, "psslai.w">;
141+
} // Predicates = [HasStdExtP, IsRV64]
142+
143+
let Predicates = [HasStdExtP] in
144+
def PLI_H : RVPUnaryImm10<0b1011000, "pli.h">;
145+
let Predicates = [HasStdExtP, IsRV64] in
146+
def PLI_W : RVPUnaryImm10<0b1011001, "pli.w">;
147+
let Predicates = [HasStdExtP] in
148+
def PLI_B : RVPUnaryImm8<0b10110100, "pli.b">;
149+
150+
let Predicates = [HasStdExtP] in {
151+
def PSEXT_H_B : RVPUnaryWUF<0b00, 0b00100, "psext.h.b">;
152+
def PSABS_H : RVPUnaryWUF<0b00, 0b00111, "psabs.h">;
153+
def PSABS_B : RVPUnaryWUF<0b10, 0b00111, "psabs.b">;
154+
} // Predicates = [HasStdExtP]
155+
let Predicates = [HasStdExtP, IsRV64] in {
156+
def PSEXT_W_B : RVPUnaryWUF<0b01, 0b00100, "psext.w.b">;
157+
def PSEXT_W_H : RVPUnaryWUF<0b01, 0b00101, "psext.w.h">;
158+
} // Predicates = [HasStdExtP, IsRV64]
159+
160+
let Predicates = [HasStdExtP] in
161+
def PLUI_H : RVPUnaryImm10<0b1111000, "plui.h", simm10_unsigned>;
162+
let Predicates = [HasStdExtP, IsRV64] in
163+
def PLUI_W : RVPUnaryImm10<0b1111001, "plui.w", simm10_unsigned>;

llvm/test/CodeGen/RISCV/attributes.ll

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -337,6 +337,7 @@
337337
; RUN: llc -mtriple=riscv64 -mattr=+sdext %s -o - | FileCheck --check-prefix=RV64SDEXT %s
338338
; RUN: llc -mtriple=riscv64 -mattr=+sdtrig %s -o - | FileCheck --check-prefix=RV64SDTRIG %s
339339
; RUN: llc -mtriple=riscv64 -mattr=+experimental-xqccmp %s -o - | FileCheck --check-prefix=RV64XQCCMP %s
340+
; RUN: llc -mtriple=riscv64 -mattr=+experimental-p %s -o - | FileCheck --check-prefix=RV64P %s
340341

341342

342343
; Tests for profile features.
@@ -526,6 +527,7 @@
526527
; RV32SUPM: .attribute 5, "rv32i2p1_supm1p0"
527528
; RV32SMCTR: .attribute 5, "rv32i2p1_smctr1p0_sscsrind1p0"
528529
; RV32SSCTR: .attribute 5, "rv32i2p1_sscsrind1p0_ssctr1p0"
530+
; RV32P: .attribute 5, "rv32i2p1_p0p14"
529531

530532
; RV64M: .attribute 5, "rv64i2p1_m2p0_zmmul1p0"
531533
; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
@@ -688,6 +690,7 @@
688690
; RV64SDEXT: .attribute 5, "rv64i2p1_sdext1p0"
689691
; RV64SDTRIG: .attribute 5, "rv64i2p1_sdtrig1p0"
690692
; RV64XQCCMP: .attribute 5, "rv64i2p1_zca1p0_xqccmp0p3"
693+
; RV64P: .attribute 5, "rv64i2p1_p0p14"
691694

692695
; RVI20U32: .attribute 5, "rv32i2p1"
693696
; RVI20U64: .attribute 5, "rv64i2p1"

llvm/test/MC/RISCV/rv32p-invalid.s

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
# RUN: not llvm-mc -triple=riscv32 --mattr=+experimental-p %s 2>&1 \
2+
# RUN: | FileCheck %s --check-prefixes=CHECK-ERROR
3+
4+
# Imm overflow
5+
pli.h a0, 0x400
6+
# CHECK-ERROR: immediate must be an integer in the range [-512, 511]
7+
plui.h a1, 0x400
8+
# CHECK-ERROR: immediate must be an integer in the range [-512, 1023]
9+
pli.b a0, 0x200
10+
# CHECK-ERROR: immediate must be an integer in the range [0, 255]
11+
12+
pslli.b a6, a7, 100
13+
# CHECK-ERROR: immediate must be an integer in the range [0, 7]
14+
pslli.h ra, sp, 100
15+
# CHECK-ERROR: immediate must be an integer in the range [0, 15]
16+
psslai.h t0, t1, 100
17+
# CHECK-ERROR: immediate must be an integer in the range [0, 15]
18+
sslai a4, a5, -1
19+
# CHECK-ERROR: immediate must be an integer in the range [0, 31]

llvm/test/MC/RISCV/rv32p-valid.s

Lines changed: 57 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,36 +1,79 @@
11
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-p -M no-aliases -show-encoding \
22
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
33
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-p < %s \
4-
# RUN: | llvm-objdump --mattr=+experimental-p -M no-aliases -d -r - \
5-
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
4+
# RUN: | llvm-objdump --mattr=+experimental-p -M no-aliases -d -r --no-print-imm-hex - \
5+
# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ,CHECK-OBJ %s
66

7-
# CHECK-ASM-AND-OBJ: sh1add a0, a1, a2
8-
# CHECK-ASM: encoding: [0x33,0xa5,0xc5,0x20]
9-
sh1add a0, a1, a2
107
# CHECK-ASM-AND-OBJ: clz a0, a1
118
# CHECK-ASM: encoding: [0x13,0x95,0x05,0x60]
129
clz a0, a1
10+
# CHECK-ASM-AND-OBJ: cls a1, a2
11+
# CHECK-ASM: encoding: [0x93,0x15,0x36,0x60]
12+
cls a1, a2
1313
# CHECK-ASM-AND-OBJ: sext.b a2, a3
1414
# CHECK-ASM: encoding: [0x13,0x96,0x46,0x60]
1515
sext.b a2, a3
1616
# CHECK-ASM-AND-OBJ: sext.h t0, t1
1717
# CHECK-ASM: encoding: [0x93,0x12,0x53,0x60]
1818
sext.h t0, t1
19+
# CHECK-ASM-AND-OBJ: abs a4, a5
20+
# CHECK-ASM: encoding: [0x13,0x97,0x77,0x60]
21+
abs a4, a5
22+
# CHECK-ASM-AND-OBJ: rev8 s0, s1
23+
# CHECK-ASM: encoding: [0x13,0xd4,0x84,0x69]
24+
rev8 s0, s1
25+
# CHECK-ASM-AND-OBJ: rev s2, s3
26+
# CHECK-ASM: encoding: [0x13,0xd9,0xf9,0x69]
27+
rev s2, s3
28+
# CHECK-ASM-AND-OBJ: sh1add a0, a1, a2
29+
# CHECK-ASM: encoding: [0x33,0xa5,0xc5,0x20]
30+
sh1add a0, a1, a2
31+
# CHECK-ASM-AND-OBJ: pack s0, s1, s2
32+
# CHECK-ASM: encoding: [0x33,0xc4,0x24,0x09]
33+
pack s0, s1, s2
1934
# CHECK-ASM-AND-OBJ: min t0, t1, t2
2035
# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
2136
min t0, t1, t2
22-
# CHECK-ASM-AND-OBJ: minu t0, t1, t2
23-
# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x0a]
24-
minu t0, t1, t2
37+
# CHECK-ASM-AND-OBJ: minu ra, sp, gp
38+
# CHECK-ASM: encoding: [0xb3,0x50,0x31,0x0a]
39+
minu ra, sp, gp
2540
# CHECK-ASM-AND-OBJ: max t3, t4, t5
2641
# CHECK-ASM: encoding: [0x33,0xee,0xee,0x0b]
2742
max t3, t4, t5
2843
# CHECK-ASM-AND-OBJ: maxu a4, a5, a6
2944
# CHECK-ASM: encoding: [0x33,0xf7,0x07,0x0b]
3045
maxu a4, a5, a6
31-
# CHECK-ASM-AND-OBJ: pack s0, s1, s2
32-
# CHECK-ASM: encoding: [0x33,0xc4,0x24,0x09]
33-
pack s0, s1, s2
34-
# CHECK-ASM-AND-OBJ: rev8 s0, s1
35-
# CHECK-ASM: encoding: [0x13,0xd4,0x84,0x69]
36-
rev8 s0, s1
46+
# CHECK-ASM-AND-OBJ: pslli.b a6, a7, 0
47+
# CHECK-ASM: encoding: [0x1b,0xa8,0x88,0x80]
48+
pslli.b a6, a7, 0
49+
# CHECK-ASM-AND-OBJ: pslli.h ra, sp, 1
50+
# CHECK-ASM: encoding: [0x9b,0x20,0x11,0x81]
51+
pslli.h ra, sp, 1
52+
# CHECK-ASM-AND-OBJ: psslai.h t0, t1, 2
53+
# CHECK-ASM: encoding: [0x9b,0x22,0x23,0xd1]
54+
psslai.h t0, t1, 2
55+
# CHECK-ASM-AND-OBJ: sslai a4, a5, 3
56+
# CHECK-ASM: encoding: [0x1b,0xa7,0x37,0xd2]
57+
sslai a4, a5, 3
58+
# CHECK-ASM-AND-OBJ: pli.h a5, 16
59+
# CHECK-ASM: encoding: [0x9b,0x27,0x10,0xb0]
60+
pli.h a5, 16
61+
# CHECK-ASM-AND-OBJ: pli.b a6, 16
62+
# CHECK-ASM: encoding: [0x1b,0x28,0x10,0xb4]
63+
pli.b a6, 16
64+
# CHECK-ASM-AND-OBJ: psext.h.b a7, a0
65+
# CHECK-ASM: encoding: [0x9b,0x28,0x45,0xe0]
66+
psext.h.b a7, a0
67+
# CHECK-ASM-AND-OBJ: psabs.h a1, a2
68+
# CHECK-ASM: encoding: [0x9b,0x25,0x76,0xe0]
69+
psabs.h a1, a2
70+
# CHECK-ASM-AND-OBJ: psabs.b t0, t1
71+
# CHECK-ASM: encoding: [0x9b,0x22,0x73,0xe4]
72+
psabs.b t0, t1
73+
# CHECK-ASM-AND-OBJ: plui.h gp, 32
74+
# CHECK-ASM: encoding: [0x9b,0x21,0x20,0xf0]
75+
plui.h gp, 32
76+
# CHECK-OBJ: plui.h gp, -412
77+
# CHECK-ASM: plui.h gp, 612
78+
# CHECK-ASM: encoding: [0x9b,0xa1,0x64,0xf0]
79+
plui.h gp, 612

llvm/test/MC/RISCV/rv64p-invalid.s

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
# RUN: not llvm-mc -triple=riscv64 --mattr=+experimental-p %s 2>&1 \
2+
# RUN: | FileCheck %s --check-prefixes=CHECK-ERROR
3+
4+
# Imm overflow
5+
pli.h a0, 0x400
6+
# CHECK-ERROR: immediate must be an integer in the range [-512, 511]
7+
plui.h a1, 0x400
8+
# CHECK-ERROR: immediate must be an integer in the range [-512, 1023]
9+
pli.w a1, -0x201
10+
# CHECK-ERROR: immediate must be an integer in the range [-512, 511]
11+
12+
pslli.b a6, a7, 100
13+
# CHECK-ERROR: immediate must be an integer in the range [0, 7]
14+
pslli.h ra, sp, 100
15+
# CHECK-ERROR: immediate must be an integer in the range [0, 15]
16+
pslli.w ra, sp, 100
17+
# CHECK-ERROR: immediate must be an integer in the range [0, 31]
18+
psslai.h t0, t1, 100
19+
# CHECK-ERROR: immediate must be an integer in the range [0, 15]
20+
psslai.w a4, a5, -1
21+
# CHECK-ERROR: error: immediate must be an integer in the range [0, 31]

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