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[RISCV][GISel] Lower G_FCONSTANT to constant pool load without F or D.
I used an IR test because it was easier than constructing different MIR test for each type of addressing.
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3 files changed

+131
-3
lines changed

3 files changed

+131
-3
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -532,6 +532,8 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
532532
}
533533
case TargetOpcode::G_JUMP_TABLE:
534534
return selectAddr(MI, MIB, MRI);
535+
case TargetOpcode::G_CONSTANT_POOL:
536+
return selectAddr(MI, MIB, MRI);
535537
case TargetOpcode::G_BRCOND: {
536538
Register LHS, RHS;
537539
RISCVCC::CondCode CC;
@@ -792,7 +794,8 @@ bool RISCVInstructionSelector::selectAddr(MachineInstr &MI,
792794
bool IsLocal,
793795
bool IsExternWeak) const {
794796
assert((MI.getOpcode() == TargetOpcode::G_GLOBAL_VALUE ||
795-
MI.getOpcode() == TargetOpcode::G_JUMP_TABLE) &&
797+
MI.getOpcode() == TargetOpcode::G_JUMP_TABLE ||
798+
MI.getOpcode() == TargetOpcode::G_CONSTANT_POOL) &&
796799
"Unexpected opcode");
797800

798801
const MachineOperand &DispMO = MI.getOperand(1);

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -188,7 +188,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
188188
.widenScalarToNextPow2(0)
189189
.clampScalar(0, sXLen, sXLen);
190190

191-
getActionDefinitionsBuilder({G_GLOBAL_VALUE, G_JUMP_TABLE}).legalFor({p0});
191+
getActionDefinitionsBuilder({G_GLOBAL_VALUE, G_JUMP_TABLE, G_CONSTANT_POOL})
192+
.legalFor({p0});
192193

193194
if (ST.hasStdExtM() || ST.hasStdExtZmmul()) {
194195
getActionDefinitionsBuilder(G_MUL)
@@ -273,7 +274,9 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
273274
getActionDefinitionsBuilder(G_IS_FPCLASS)
274275
.customIf(all(typeIs(0, s1), typeIsScalarFPArith(1, ST)));
275276

276-
getActionDefinitionsBuilder(G_FCONSTANT).legalIf(typeIsScalarFPArith(0, ST));
277+
getActionDefinitionsBuilder(G_FCONSTANT)
278+
.legalIf(typeIsScalarFPArith(0, ST))
279+
.lowerFor({s32, s64});
277280

278281
getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
279282
.legalIf(all(typeInSet(0, {s32, sXLen}), typeIsScalarFPArith(1, ST)))

‎llvm/test/CodeGen/RISCV/GlobalISel/constantpool.ll

Lines changed: 122 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,122 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2+
; RUN: llc < %s -mtriple=riscv32 -global-isel -code-model=small \
3+
; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=RV32-SMALL
4+
; RUN: llc < %s -mtriple=riscv32 -global-isel -code-model=medium \
5+
; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=RV32-MEDIUM
6+
; RUN: llc < %s -mtriple=riscv32 -global-isel -relocation-model=pic \
7+
; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=RV32-PIC
8+
; RUN: llc < %s -mtriple=riscv64 -global-isel -code-model=small \
9+
; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=RV64-SMALL
10+
; RUN: llc < %s -mtriple=riscv64 -global-isel -code-model=medium \
11+
; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=RV64-MEDIUM
12+
; RUN: llc < %s -mtriple=riscv64 -global-isel -relocation-model=pic \
13+
; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=RV64-PIC
14+
15+
define void @constpool_f32(ptr %p) {
16+
; RV32-SMALL-LABEL: constpool_f32:
17+
; RV32-SMALL: # %bb.0:
18+
; RV32-SMALL-NEXT: lui a1, %hi(.LCPI0_0)
19+
; RV32-SMALL-NEXT: lw a1, %lo(.LCPI0_0)(a1)
20+
; RV32-SMALL-NEXT: sw a1, 0(a0)
21+
; RV32-SMALL-NEXT: ret
22+
;
23+
; RV32-MEDIUM-LABEL: constpool_f32:
24+
; RV32-MEDIUM: # %bb.0:
25+
; RV32-MEDIUM-NEXT: .Lpcrel_hi0:
26+
; RV32-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
27+
; RV32-MEDIUM-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi0)(a1)
28+
; RV32-MEDIUM-NEXT: sw a1, 0(a0)
29+
; RV32-MEDIUM-NEXT: ret
30+
;
31+
; RV32-PIC-LABEL: constpool_f32:
32+
; RV32-PIC: # %bb.0:
33+
; RV32-PIC-NEXT: .Lpcrel_hi0:
34+
; RV32-PIC-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
35+
; RV32-PIC-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi0)(a1)
36+
; RV32-PIC-NEXT: sw a1, 0(a0)
37+
; RV32-PIC-NEXT: ret
38+
;
39+
; RV64-SMALL-LABEL: constpool_f32:
40+
; RV64-SMALL: # %bb.0:
41+
; RV64-SMALL-NEXT: lui a1, %hi(.LCPI0_0)
42+
; RV64-SMALL-NEXT: lw a1, %lo(.LCPI0_0)(a1)
43+
; RV64-SMALL-NEXT: sw a1, 0(a0)
44+
; RV64-SMALL-NEXT: ret
45+
;
46+
; RV64-MEDIUM-LABEL: constpool_f32:
47+
; RV64-MEDIUM: # %bb.0:
48+
; RV64-MEDIUM-NEXT: .Lpcrel_hi0:
49+
; RV64-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
50+
; RV64-MEDIUM-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi0)(a1)
51+
; RV64-MEDIUM-NEXT: sw a1, 0(a0)
52+
; RV64-MEDIUM-NEXT: ret
53+
;
54+
; RV64-PIC-LABEL: constpool_f32:
55+
; RV64-PIC: # %bb.0:
56+
; RV64-PIC-NEXT: .Lpcrel_hi0:
57+
; RV64-PIC-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
58+
; RV64-PIC-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi0)(a1)
59+
; RV64-PIC-NEXT: sw a1, 0(a0)
60+
; RV64-PIC-NEXT: ret
61+
store float 1.0, ptr %p
62+
ret void
63+
}
64+
65+
define void @constpool_f64(ptr %p) {
66+
; RV32-SMALL-LABEL: constpool_f64:
67+
; RV32-SMALL: # %bb.0:
68+
; RV32-SMALL-NEXT: lui a1, %hi(.LCPI1_0)
69+
; RV32-SMALL-NEXT: addi a1, a1, %lo(.LCPI1_0)
70+
; RV32-SMALL-NEXT: lw a2, 0(a1)
71+
; RV32-SMALL-NEXT: lw a1, 4(a1)
72+
; RV32-SMALL-NEXT: sw a2, 0(a0)
73+
; RV32-SMALL-NEXT: sw a1, 4(a0)
74+
; RV32-SMALL-NEXT: ret
75+
;
76+
; RV32-MEDIUM-LABEL: constpool_f64:
77+
; RV32-MEDIUM: # %bb.0:
78+
; RV32-MEDIUM-NEXT: .Lpcrel_hi1:
79+
; RV32-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
80+
; RV32-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi1)
81+
; RV32-MEDIUM-NEXT: lw a2, 0(a1)
82+
; RV32-MEDIUM-NEXT: lw a1, 4(a1)
83+
; RV32-MEDIUM-NEXT: sw a2, 0(a0)
84+
; RV32-MEDIUM-NEXT: sw a1, 4(a0)
85+
; RV32-MEDIUM-NEXT: ret
86+
;
87+
; RV32-PIC-LABEL: constpool_f64:
88+
; RV32-PIC: # %bb.0:
89+
; RV32-PIC-NEXT: .Lpcrel_hi1:
90+
; RV32-PIC-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
91+
; RV32-PIC-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi1)
92+
; RV32-PIC-NEXT: lw a2, 0(a1)
93+
; RV32-PIC-NEXT: lw a1, 4(a1)
94+
; RV32-PIC-NEXT: sw a2, 0(a0)
95+
; RV32-PIC-NEXT: sw a1, 4(a0)
96+
; RV32-PIC-NEXT: ret
97+
;
98+
; RV64-SMALL-LABEL: constpool_f64:
99+
; RV64-SMALL: # %bb.0:
100+
; RV64-SMALL-NEXT: lui a1, %hi(.LCPI1_0)
101+
; RV64-SMALL-NEXT: ld a1, %lo(.LCPI1_0)(a1)
102+
; RV64-SMALL-NEXT: sd a1, 0(a0)
103+
; RV64-SMALL-NEXT: ret
104+
;
105+
; RV64-MEDIUM-LABEL: constpool_f64:
106+
; RV64-MEDIUM: # %bb.0:
107+
; RV64-MEDIUM-NEXT: .Lpcrel_hi1:
108+
; RV64-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
109+
; RV64-MEDIUM-NEXT: ld a1, %pcrel_lo(.Lpcrel_hi1)(a1)
110+
; RV64-MEDIUM-NEXT: sd a1, 0(a0)
111+
; RV64-MEDIUM-NEXT: ret
112+
;
113+
; RV64-PIC-LABEL: constpool_f64:
114+
; RV64-PIC: # %bb.0:
115+
; RV64-PIC-NEXT: .Lpcrel_hi1:
116+
; RV64-PIC-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
117+
; RV64-PIC-NEXT: ld a1, %pcrel_lo(.Lpcrel_hi1)(a1)
118+
; RV64-PIC-NEXT: sd a1, 0(a0)
119+
; RV64-PIC-NEXT: ret
120+
store double 1.0, ptr %p
121+
ret void
122+
}

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