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AMDGPU: Copy correct predicates for SDWA reals
There are a lot of messes in the special case predicate handling. Currently broad let blocks override specific predicates with more general cases. For instructions with SDWA, the HasSDWA predicate was overriding the SubtargetPredicate for the instruction. This fixes enough to properly disallow new instructions that support SDWA on older targets.
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+27
-23
lines changed

5 files changed

+27
-23
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPU.td

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2103,8 +2103,10 @@ def NotHasMinMaxDenormModes : Predicate<"!Subtarget->supportsMinMaxDenormModes()
21032103

21042104
def HasFminFmaxLegacy : Predicate<"Subtarget->hasFminFmaxLegacy()">;
21052105

2106-
def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
2107-
AssemblerPredicate<(all_of FeatureSDWA, FeatureVolcanicIslands)>;
2106+
def HasSDWA : Predicate<"Subtarget->hasSDWA()">;
2107+
2108+
def HasSDWA8 : Predicate<"Subtarget->hasSDWA()">,
2109+
AssemblerPredicate<(all_of (not FeatureGFX9Insts), FeatureSDWA)>;
21082110

21092111
def HasSDWA9 :
21102112
Predicate<"Subtarget->hasSDWA()">,

‎llvm/lib/Target/AMDGPU/VOP1Instructions.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1268,7 +1268,7 @@ multiclass VOP1_Real_vi <bits<10> op> {
12681268

12691269
if !cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA then
12701270
def _sdwa_vi :
1271-
VOP_SDWA_Real <!cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa")>,
1271+
VOP_SDWA8_Real <!cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa")>,
12721272
VOP1_SDWAe <op{7-0}, !cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
12731273

12741274
if !cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9 then
@@ -1474,7 +1474,7 @@ def : GCNPat <
14741474
// GFX9
14751475
//===----------------------------------------------------------------------===//
14761476

1477-
let AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" in {
1477+
let DecoderNamespace = "GFX9" in {
14781478
multiclass VOP1_Real_gfx9 <bits<10> op> {
14791479
defm NAME : VOP1_Real_e32e64_vi <op>;
14801480

‎llvm/lib/Target/AMDGPU/VOP2Instructions.td

Lines changed: 14 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -766,16 +766,16 @@ defm V_SUBB_U32 : VOP2bInst <"v_subb_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "
766766
defm V_SUBBREV_U32 : VOP2bInst <"v_subbrev_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32">;
767767

768768

769-
let SubtargetPredicate = HasAddNoCarryInsts, isReMaterializable = 1 in {
769+
let SubtargetPredicate = HasAddNoCarryInsts, isReMaterializable = 1 in {
770770
defm V_SUB_U32 : VOP2Inst <"v_sub_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32">;
771771
defm V_SUBREV_U32 : VOP2Inst <"v_subrev_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32">;
772772
}
773773

774-
let SubtargetPredicate = HasAddNoCarryInsts, isReMaterializable = 1, isAdd = 1 in {
774+
let SubtargetPredicate = HasAddNoCarryInsts, isReMaterializable = 1, isAdd = 1 in {
775775
defm V_ADD_U32 : VOP2Inst_VOPD <"v_add_u32", VOP_I32_I32_I32_ARITH, 0x10, "v_add_nc_u32", null_frag, "v_add_u32">;
776776
}
777777

778-
let isAdd = 1 in {
778+
let isAdd = 1 in {
779779
defm V_ADD_CO_U32 : VOP2bInst <"v_add_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_add_co_u32">;
780780
defm V_ADDC_U32 : VOP2bInst <"v_addc_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_addc_u32">;
781781
}
@@ -2290,10 +2290,10 @@ multiclass Base_VOP2_Real_e32e64_vi <bits<6> op> :
22902290

22912291
} // End AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8"
22922292

2293-
multiclass VOP2_SDWA_Real <bits<6> op> {
2293+
multiclass VOP2_SDWA8_Real <bits<6> op> {
22942294
if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA then
22952295
def _sdwa_vi :
2296-
VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
2296+
VOP_SDWA8_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
22972297
VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
22982298
}
22992299

@@ -2321,7 +2321,7 @@ multiclass VOP2be_Real_e32e64_vi_only <bits<6> op, string OpName, string AsmName
23212321
}
23222322
if !cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtSDWA then
23232323
def _sdwa_vi :
2324-
VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>,
2324+
VOP_SDWA8_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>,
23252325
VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> {
23262326
VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa");
23272327
let AsmString = AsmName # ps.AsmOperands;
@@ -2337,7 +2337,7 @@ multiclass VOP2be_Real_e32e64_vi_only <bits<6> op, string OpName, string AsmName
23372337

23382338
} // End AssemblerPredicate = isGFX8Only, DecoderNamespace = "GFX8"
23392339

2340-
let AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" in {
2340+
let DecoderNamespace = "GFX9" in {
23412341

23422342
multiclass VOP2be_Real_e32e64_gfx9 <bits<6> op, string OpName, string AsmName> {
23432343
def _e32_gfx9 :
@@ -2386,10 +2386,10 @@ multiclass VOP2_Real_e32e64_gfx9 <bits<6> op> {
23862386
VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>;
23872387
}
23882388

2389-
} // End AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9"
2389+
} // End DecoderNamespace = "GFX9"
23902390

23912391
multiclass VOP2_Real_e32e64_vi <bits<6> op> :
2392-
Base_VOP2_Real_e32e64_vi<op>, VOP2_SDWA_Real<op>, VOP2_SDWA9_Real<op> {
2392+
Base_VOP2_Real_e32e64_vi<op>, VOP2_SDWA8_Real<op>, VOP2_SDWA9_Real<op> {
23932393

23942394
if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP then
23952395
def _dpp_vi :
@@ -2401,7 +2401,7 @@ defm V_CNDMASK_B32 : VOP2_Real_e32e64_vi <0x0>;
24012401
defm V_ADD_F32 : VOP2_Real_e32e64_vi <0x1>;
24022402
defm V_SUB_F32 : VOP2_Real_e32e64_vi <0x2>;
24032403
defm V_SUBREV_F32 : VOP2_Real_e32e64_vi <0x3>;
2404-
let AssemblerPredicate = isGCN3ExcludingGFX90A in
2404+
let OtherPredicates = [isGCN3ExcludingGFX90A] in
24052405
defm V_MUL_LEGACY_F32 : VOP2_Real_e32e64_vi <0x4>;
24062406
defm V_MUL_F32 : VOP2_Real_e32e64_vi <0x5>;
24072407
defm V_MUL_I32_I24 : VOP2_Real_e32e64_vi <0x6>;
@@ -2431,6 +2431,7 @@ defm V_ADDC_U32 : VOP2be_Real_e32e64_vi_only <0x1c, "V_ADDC_U32", "
24312431
defm V_SUBB_U32 : VOP2be_Real_e32e64_vi_only <0x1d, "V_SUBB_U32", "v_subb_u32">;
24322432
defm V_SUBBREV_U32 : VOP2be_Real_e32e64_vi_only <0x1e, "V_SUBBREV_U32", "v_subbrev_u32">;
24332433

2434+
let AssemblerPredicate = isGFX9Only in {
24342435
defm V_ADD_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x19, "V_ADD_CO_U32", "v_add_co_u32">;
24352436
defm V_SUB_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1a, "V_SUB_CO_U32", "v_sub_co_u32">;
24362437
defm V_SUBREV_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1b, "V_SUBREV_CO_U32", "v_subrev_co_u32">;
@@ -2441,6 +2442,7 @@ defm V_SUBBREV_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1e, "V_SUBBREV_U32", "v_s
24412442
defm V_ADD_U32 : VOP2_Real_e32e64_gfx9 <0x34>;
24422443
defm V_SUB_U32 : VOP2_Real_e32e64_gfx9 <0x35>;
24432444
defm V_SUBREV_U32 : VOP2_Real_e32e64_gfx9 <0x36>;
2445+
} // End AssemblerPredicate = isGFX9Only
24442446

24452447
defm V_BFM_B32 : VOP2_Real_e64only_vi <0x293>;
24462448
defm V_BCNT_U32_B32 : VOP2_Real_e64only_vi <0x28b>;
@@ -2518,7 +2520,7 @@ defm V_XNOR_B32 : VOP2_Real_e32e64_vi <0x3d>;
25182520

25192521
} // End SubtargetPredicate = HasDLInsts
25202522

2521-
let AssemblerPredicate = isGFX90APlus, DecoderNamespace = "GFX90A" in {
2523+
let DecoderNamespace = "GFX90A" in {
25222524
multiclass VOP2_Real_e32_gfx90a <bits<6> op> {
25232525
def _e32_gfx90a :
25242526
VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX90A>,
@@ -2551,7 +2553,7 @@ let SubtargetPredicate = HasFmacF64Inst in {
25512553
defm V_FMAC_F64 : VOP2_Real_e32e64_gfx90a <0x4>;
25522554
} // End SubtargetPredicate = HasFmacF64Inst
25532555

2554-
let SubtargetPredicate = isGFX90APlus, IsSingle = 1 in {
2556+
let IsSingle = 1 in {
25552557
defm V_MUL_LEGACY_F32 : VOP2_Real_e64_gfx90a <0x2a1>;
25562558
}
25572559

‎llvm/lib/Target/AMDGPU/VOPCInstructions.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2290,7 +2290,7 @@ multiclass VOPC_Real_vi <bits<10> op> {
22902290

22912291
if !cast<VOPC_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA then
22922292
def _sdwa_vi :
2293-
VOP_SDWA_Real <!cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa")>,
2293+
VOP_SDWA8_Real <!cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa")>,
22942294
VOPC_SDWAe <op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
22952295

22962296
if !cast<VOPC_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9 then

‎llvm/lib/Target/AMDGPU/VOPInstructions.td

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -650,15 +650,15 @@ class VOP_SDWA_Pseudo <string opName, VOPProfile P, list<dag> pattern=[]> :
650650
let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);
651651

652652
let SubtargetPredicate = HasSDWA;
653-
let AssemblerPredicate = HasSDWA;
653+
//let AssemblerPredicate = HasSDWA;
654654
let AsmVariantName = !if(P.HasExtSDWA, AMDGPUAsmVariants.SDWA,
655655
AMDGPUAsmVariants.Disable);
656656
let DecoderNamespace = "GFX8";
657657

658658
VOPProfile Pfl = P;
659659
}
660660

661-
class VOP_SDWA_Real <VOP_SDWA_Pseudo ps> :
661+
class VOP_SDWA8_Real <VOP_SDWA_Pseudo ps> :
662662
InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
663663
SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA> {
664664

@@ -676,7 +676,7 @@ class VOP_SDWA_Real <VOP_SDWA_Pseudo ps> :
676676

677677
// Copy relevant pseudo op flags
678678
let SubtargetPredicate = ps.SubtargetPredicate;
679-
let AssemblerPredicate = ps.AssemblerPredicate;
679+
let AssemblerPredicate = HasSDWA8;
680680
let AsmMatchConverter = ps.AsmMatchConverter;
681681
let AsmVariantName = ps.AsmVariantName;
682682
let UseNamedOperandTable = ps.UseNamedOperandTable;
@@ -708,7 +708,7 @@ class Base_VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
708708
let Constraints = ps.Constraints;
709709
let DisableEncoding = ps.DisableEncoding;
710710

711-
let SubtargetPredicate = HasSDWA9;
711+
let SubtargetPredicate = ps.SubtargetPredicate;
712712
let AssemblerPredicate = HasSDWA9;
713713
let OtherPredicates = ps.OtherPredicates;
714714
let AsmVariantName = !if(ps.Pfl.HasExtSDWA9, AMDGPUAsmVariants.SDWA9,
@@ -735,7 +735,7 @@ class VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
735735
SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA9>;
736736

737737
class Base_VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> : Base_VOP_SDWA9_Real<ps> {
738-
let SubtargetPredicate = HasSDWA10;
738+
let SubtargetPredicate = ps.SubtargetPredicate;
739739
let AssemblerPredicate = HasSDWA10;
740740
let DecoderNamespace = "GFX10";
741741
}
@@ -1508,7 +1508,7 @@ class VOP3_DPP16_t16_Helper<bits<10> op, VOP_DPP_Pseudo ps,
15081508
let SchedRW = ps.SchedRW;
15091509
let Uses = ps.Uses;
15101510
let AssemblerPredicate = HasDPP16;
1511-
let SubtargetPredicate = HasDPP16;
1511+
let SubtargetPredicate = ps.SubtargetPredicate;
15121512
let OtherPredicates = ps.OtherPredicates;
15131513
}
15141514

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