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[RISCV][GISel] Add isel patterns for i16 load/store (#116293)
In order to support f16 load/store we need to make load/stores with s16 register type legal. If regbank selection doesn't pick the FPR bank, we'll be left with a GPR load or store which we don't have isel patterns for from SelectionDAG. In order to add the patterns we need to make i16 a legal type for the GPR register class. Tests are currently disabling the legality check because I haven't update the legalizer yet.
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‎llvm/lib/Target/RISCV/RISCVGISel.td

Lines changed: 11 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -169,6 +169,11 @@ def : LdPat<load, LD, PtrVT>;
169169
def : StPat<store, SD, GPR, PtrVT>;
170170
}
171171

172+
// Load and store patterns for i16, needed because Zfh makes s16 load/store
173+
// legal and regbank select may not constrain registers to FP.
174+
def : LdPat<load, LH, i16>;
175+
def : StPat<store, SH, GPR, i16>;
176+
172177
//===----------------------------------------------------------------------===//
173178
// RV64 i32 patterns not used by SelectionDAG
174179
//===----------------------------------------------------------------------===//
@@ -187,22 +192,22 @@ def : LdPat<extloadi16, LH, i32>;
187192
def : StPat<truncstorei8, SB, GPR, i32>;
188193
def : StPat<truncstorei16, SH, GPR, i32>;
189194

190-
def : Pat<(anyext GPR:$src), (COPY GPR:$src)>;
191-
def : Pat<(sext GPR:$src), (ADDIW GPR:$src, 0)>;
192-
def : Pat<(trunc GPR:$src), (COPY GPR:$src)>;
195+
def : Pat<(anyext (i32 GPR:$src)), (COPY GPR:$src)>;
196+
def : Pat<(sext (i32 GPR:$src)), (ADDIW GPR:$src, 0)>;
197+
def : Pat<(i32 (trunc GPR:$src)), (COPY GPR:$src)>;
193198

194199
// Use sext if the sign bit of the input is 0.
195-
def : Pat<(zext_is_sext GPR:$src), (ADDIW GPR:$src, 0)>;
200+
def : Pat<(zext_is_sext (i32 GPR:$src)), (ADDIW GPR:$src, 0)>;
196201
}
197202

198203
let Predicates = [IsRV64, NotHasStdExtZba] in {
199-
def : Pat<(zext GPR:$src), (SRLI (i64 (SLLI GPR:$src, 32)), 32)>;
204+
def : Pat<(zext (i32 GPR:$src)), (SRLI (i64 (SLLI GPR:$src, 32)), 32)>;
200205
}
201206

202207
//===----------------------------------------------------------------------===//
203208
// Zb* RV64 i32 patterns not used by SelectionDAG.
204209
//===----------------------------------------------------------------------===//
205210

206211
let Predicates = [HasStdExtZba, IsRV64] in {
207-
def : Pat<(zext GPR:$src), (ADD_UW GPR:$src, (XLenVT X0))>;
212+
def : Pat<(zext (i32 GPR:$src)), (ADD_UW GPR:$src, (XLenVT X0))>;
208213
}

‎llvm/lib/Target/RISCV/RISCVRegisterInfo.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -231,7 +231,7 @@ class RISCVRegisterClass<list<ValueType> regTypes, int align, dag regList>
231231
}
232232

233233
class GPRRegisterClass<dag regList>
234-
: RISCVRegisterClass<[XLenVT, XLenFVT, i32], 32, regList> {
234+
: RISCVRegisterClass<[XLenVT, XLenFVT, i32, i16], 32, regList> {
235235
let RegInfos = XLenRI;
236236
}
237237

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir

Lines changed: 24 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \
3-
# RUN: | FileCheck %s
3+
# RUN: -disable-gisel-legality-check | FileCheck %s
44

55
---
66
name: load_i8
@@ -45,6 +45,29 @@ body: |
4545
$x10 = COPY %1(s32)
4646
PseudoRET implicit $x10
4747
48+
...
49+
---
50+
name: load_i16_i16
51+
legalized: true
52+
regBankSelected: true
53+
tracksRegLiveness: true
54+
body: |
55+
bb.0:
56+
liveins: $x10
57+
58+
; CHECK-LABEL: name: load_i16_i16
59+
; CHECK: liveins: $x10
60+
; CHECK-NEXT: {{ $}}
61+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
62+
; CHECK-NEXT: [[LH:%[0-9]+]]:gpr = LH [[COPY]], 0 :: (load (s16))
63+
; CHECK-NEXT: $x10 = COPY [[LH]]
64+
; CHECK-NEXT: PseudoRET implicit $x10
65+
%0:gprb(p0) = COPY $x10
66+
%1:gprb(s16) = G_LOAD %0(p0) :: (load (s16))
67+
%2:gprb(s32) = G_ANYEXT %1
68+
$x10 = COPY %2(s32)
69+
PseudoRET implicit $x10
70+
4871
...
4972
---
5073
name: load_i32

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir

Lines changed: 24 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \
3-
# RUN: | FileCheck %s
3+
# RUN: -disable-gisel-legality-check | FileCheck %s
44

55
---
66
name: load_i8_i64
@@ -45,6 +45,29 @@ body: |
4545
$x10 = COPY %1(s64)
4646
PseudoRET implicit $x10
4747
48+
...
49+
---
50+
name: load_i16_i16
51+
legalized: true
52+
regBankSelected: true
53+
tracksRegLiveness: true
54+
body: |
55+
bb.0:
56+
liveins: $x10
57+
58+
; CHECK-LABEL: name: load_i16_i16
59+
; CHECK: liveins: $x10
60+
; CHECK-NEXT: {{ $}}
61+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
62+
; CHECK-NEXT: [[LH:%[0-9]+]]:gpr = LH [[COPY]], 0 :: (load (s16))
63+
; CHECK-NEXT: $x10 = COPY [[LH]]
64+
; CHECK-NEXT: PseudoRET implicit $x10
65+
%0:gprb(p0) = COPY $x10
66+
%1:gprb(s16) = G_LOAD %0(p0) :: (load (s16))
67+
%2:gprb(s64) = G_ANYEXT %1
68+
$x10 = COPY %2(s64)
69+
PseudoRET implicit $x10
70+
4871
...
4972
---
5073
name: load_i32_i64

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv32.mir

Lines changed: 24 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \
3-
# RUN: | FileCheck %s
3+
# RUN: -disable-gisel-legality-check | FileCheck %s
44
#
55
---
66
name: store_i8
@@ -45,6 +45,29 @@ body: |
4545
G_STORE %0(s32), %1(p0) :: (store (s16))
4646
PseudoRET
4747
48+
...
49+
---
50+
name: store_i16_i16
51+
legalized: true
52+
regBankSelected: true
53+
tracksRegLiveness: true
54+
body: |
55+
bb.0:
56+
liveins: $x10, $x11
57+
58+
; CHECK-LABEL: name: store_i16_i16
59+
; CHECK: liveins: $x10, $x11
60+
; CHECK-NEXT: {{ $}}
61+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
62+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
63+
; CHECK-NEXT: SH [[COPY]], [[COPY1]], 0 :: (store (s16))
64+
; CHECK-NEXT: PseudoRET
65+
%0:gprb(s32) = COPY $x10
66+
%1:gprb(p0) = COPY $x11
67+
%2:gprb(s16) = G_TRUNC %0
68+
G_STORE %2(s16), %1(p0) :: (store (s16))
69+
PseudoRET
70+
4871
...
4972
---
5073
name: store_i32

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv64.mir

Lines changed: 24 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \
3-
# RUN: | FileCheck %s
3+
# RUN: -disable-gisel-legality-check | FileCheck %s
44

55
---
66
name: store_i8_i64
@@ -45,6 +45,29 @@ body: |
4545
G_STORE %0(s64), %1(p0) :: (store (s16))
4646
PseudoRET
4747
48+
...
49+
---
50+
name: store_i16_i16
51+
legalized: true
52+
regBankSelected: true
53+
tracksRegLiveness: true
54+
body: |
55+
bb.0:
56+
liveins: $x10, $x11
57+
58+
; CHECK-LABEL: name: store_i16_i16
59+
; CHECK: liveins: $x10, $x11
60+
; CHECK-NEXT: {{ $}}
61+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
62+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
63+
; CHECK-NEXT: SH [[COPY]], [[COPY1]], 0 :: (store (s16))
64+
; CHECK-NEXT: PseudoRET
65+
%0:gprb(s64) = COPY $x10
66+
%1:gprb(p0) = COPY $x11
67+
%2:gprb(s16) = G_TRUNC %0
68+
G_STORE %2(s16), %1(p0) :: (store (s16))
69+
PseudoRET
70+
4871
...
4972
---
5073
name: store_i32_i64

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