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[PowerPC] Enhance the selection(ISD::VSELECT) of vector type
To make ISD::VSELECT available(legal) so long as there are altivec instruction, otherwise it's default behavior is expanding, which is legalized at type-legalization phase. Use xxsel to match vselect if vsx is open, or use vsel. Differential Revision: https://reviews.llvm.org/D49531 llvm-svn: 346824
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5 files changed

+133
-20
lines changed

5 files changed

+133
-20
lines changed

‎llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -4736,14 +4736,6 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
47364736
CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops);
47374737
return;
47384738
}
4739-
case ISD::VSELECT:
4740-
if (PPCSubTarget->hasVSX()) {
4741-
SDValue Ops[] = { N->getOperand(2), N->getOperand(1), N->getOperand(0) };
4742-
CurDAG->SelectNodeTo(N, PPC::XXSEL, N->getValueType(0), Ops);
4743-
return;
4744-
}
4745-
break;
4746-
47474739
case ISD::VECTOR_SHUFFLE:
47484740
if (PPCSubTarget->hasVSX() && (N->getValueType(0) == MVT::v2f64 ||
47494741
N->getValueType(0) == MVT::v2i64)) {

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -586,6 +586,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
586586
AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
587587
setOperationAction(ISD::SELECT, VT, Promote);
588588
AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
589+
setOperationAction(ISD::VSELECT, VT, Legal);
589590
setOperationAction(ISD::SELECT_CC, VT, Promote);
590591
AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
591592
setOperationAction(ISD::STORE, VT, Promote);
@@ -626,7 +627,6 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
626627
setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
627628
setOperationAction(ISD::FPOW, VT, Expand);
628629
setOperationAction(ISD::BSWAP, VT, Expand);
629-
setOperationAction(ISD::VSELECT, VT, Expand);
630630
setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
631631
setOperationAction(ISD::ROTL, VT, Expand);
632632
setOperationAction(ISD::ROTR, VT, Expand);
@@ -727,12 +727,6 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
727727
setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
728728
setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
729729

730-
setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
731-
setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
732-
setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
733-
setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
734-
setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
735-
736730
// Share the Altivec comparison restrictions.
737731
setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
738732
setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);

‎llvm/lib/Target/PowerPC/PPCInstrAltivec.td

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1051,6 +1051,20 @@ def : Pat<(v4f32 (ftrunc v4f32:$vA)),
10511051
def : Pat<(v4f32 (fnearbyint v4f32:$vA)),
10521052
(VRFIN $vA)>;
10531053

1054+
// Vector selection
1055+
def : Pat<(v16i8 (vselect v16i8:$vA, v16i8:$vB, v16i8:$vC)),
1056+
(VSEL $vC, $vB, $vA)>;
1057+
def : Pat<(v8i16 (vselect v8i16:$vA, v8i16:$vB, v8i16:$vC)),
1058+
(VSEL $vC, $vB, $vA)>;
1059+
def : Pat<(v4i32 (vselect v4i32:$vA, v4i32:$vB, v4i32:$vC)),
1060+
(VSEL $vC, $vB, $vA)>;
1061+
def : Pat<(v2i64 (vselect v2i64:$vA, v2i64:$vB, v2i64:$vC)),
1062+
(VSEL $vC, $vB, $vA)>;
1063+
def : Pat<(v4f32 (vselect v4i32:$vA, v4f32:$vB, v4f32:$vC)),
1064+
(VSEL $vC, $vB, $vA)>;
1065+
def : Pat<(v2f64 (vselect v2i64:$vA, v2f64:$vB, v2f64:$vC)),
1066+
(VSEL $vC, $vB, $vA)>;
1067+
10541068
} // end HasAltivec
10551069

10561070
def HasP8Altivec : Predicate<"PPCSubTarget->hasP8Altivec()">;

‎llvm/lib/Target/PowerPC/PPCInstrVSX.td

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1152,6 +1152,26 @@ def : Pat<(int_ppc_vsx_xvrsqrtesp v4f32:$A),
11521152
def : Pat<(int_ppc_vsx_xvrsqrtedp v2f64:$A),
11531153
(XVRSQRTEDP $A)>;
11541154

1155+
// Vector selection
1156+
def : Pat<(v16i8 (vselect v16i8:$vA, v16i8:$vB, v16i8:$vC)),
1157+
(COPY_TO_REGCLASS
1158+
(XXSEL (COPY_TO_REGCLASS $vC, VSRC),
1159+
(COPY_TO_REGCLASS $vB, VSRC),
1160+
(COPY_TO_REGCLASS $vA, VSRC)), VRRC)>;
1161+
def : Pat<(v8i16 (vselect v8i16:$vA, v8i16:$vB, v8i16:$vC)),
1162+
(COPY_TO_REGCLASS
1163+
(XXSEL (COPY_TO_REGCLASS $vC, VSRC),
1164+
(COPY_TO_REGCLASS $vB, VSRC),
1165+
(COPY_TO_REGCLASS $vA, VSRC)), VRRC)>;
1166+
def : Pat<(vselect v4i32:$vA, v4i32:$vB, v4i32:$vC),
1167+
(XXSEL $vC, $vB, $vA)>;
1168+
def : Pat<(vselect v2i64:$vA, v2i64:$vB, v2i64:$vC),
1169+
(XXSEL $vC, $vB, $vA)>;
1170+
def : Pat<(vselect v4i32:$vA, v4f32:$vB, v4f32:$vC),
1171+
(XXSEL $vC, $vB, $vA)>;
1172+
def : Pat<(vselect v2i64:$vA, v2f64:$vB, v2f64:$vC),
1173+
(XXSEL $vC, $vB, $vA)>;
1174+
11551175
let Predicates = [IsLittleEndian] in {
11561176
def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
11571177
(f64 (XSCVSXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;

‎llvm/test/CodeGen/PowerPC/vec_select.ll

Lines changed: 98 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,100 @@
1-
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-linux-gnu -mattr=+altivec | FileCheck %s
1+
; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64-linux-gnu -mcpu=pwr8 -mattr=+vsx | FileCheck %s -check-prefix=CHECK-VSX
2+
; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s -check-prefix=CHECK-NOVSX
3+
; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 -mattr=+vsx | FileCheck %s -check-prefix=CHECK-VSX
4+
; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s -check-prefix=CHECK-NOVSX
25

3-
; CHECK: vsel_float
4-
define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
5-
%vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %v1, <4 x float> %v2
6-
ret <4 x float> %vsel
6+
define <4 x float> @test1(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
7+
entry:
8+
%m = fcmp oeq <4 x float> %c, %d
9+
%v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
10+
ret <4 x float> %v
711
}
12+
; CHECK-VSX-LABLE: test1
13+
; CHECK-VSX: xvcmpeqsp [[REG1:(vs|v)[0-9]+]], v4, v5
14+
; CHECK-VSX: xxsel v2, v3, v2, [[REG1]]
15+
; CHECK-VSX: blr
16+
17+
; CHECK-NOVSX-LABLE: test1
18+
; CHECK-NOVSX: vcmpeqfp v[[REG1:[0-9]+]], v4, v5
19+
; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]]
20+
; CHECK-NOVSX: blr
21+
22+
define <2 x double> @test2(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) {
23+
entry:
24+
%m = fcmp oeq <2 x double> %c, %d
25+
%v = select <2 x i1> %m, <2 x double> %a, <2 x double> %b
26+
ret <2 x double> %v
27+
}
28+
; CHECK-VSX-LABLE: test2
29+
; CHECK-VSX: xvcmpeqdp [[REG1:(vs|v)[0-9]+]], v4, v5
30+
; CHECK-VSX: xxsel v2, v3, v2, [[REG1]]
31+
; CHECK-VSX: blr
32+
33+
; CHECK-NOVSX-LABLE: test2
34+
; CHECK-NOVSX: fcmp
35+
; CHECK-NOVSX: fcmp
36+
; CHECK-NOVSX: blr
37+
38+
define <16 x i8> @test3(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {
39+
entry:
40+
%m = icmp eq <16 x i8> %c, %d
41+
%v = select <16 x i1> %m, <16 x i8> %a, <16 x i8> %b
42+
ret <16 x i8> %v
43+
}
44+
; CHECK-VSX-LABLE: test3
45+
; CHECK-VSX: vcmpequb v[[REG1:[0-9]+]], v4, v5
46+
; CHECK-VSX: xxsel v2, v3, v2, v[[REG1]]
47+
; CHECK-VSX: blr
48+
49+
; CHECK-NOVSX-LABLE: test3
50+
; CHECK-NOVSX: vcmpequb v[[REG1:[0-9]+]], v4, v5
51+
; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]]
52+
; CHECK-NOVSX: blr
53+
54+
define <8 x i16> @test4(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) {
55+
entry:
56+
%m = icmp eq <8 x i16> %c, %d
57+
%v = select <8 x i1> %m, <8 x i16> %a, <8 x i16> %b
58+
ret <8 x i16> %v
59+
}
60+
; CHECK-VSX-LABLE: test4
61+
; CHECK-VSX: vcmpequh v[[REG1:[0-9]+]], v4, v5
62+
; CHECK-VSX: xxsel v2, v3, v2, v[[REG1]]
63+
; CHECK-VSX: blr
64+
65+
; CHECK-NOVSX-LABLE: test4
66+
; CHECK-NOVSX: vcmpequh v[[REG1:[0-9]+]], v4, v5
67+
; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]]
68+
; CHECK-NOVSX: blr
69+
70+
define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
71+
entry:
72+
%m = icmp eq <4 x i32> %c, %d
73+
%v = select <4 x i1> %m, <4 x i32> %a, <4 x i32> %b
74+
ret <4 x i32> %v
75+
}
76+
; CHECK-VSX-LABLE: test5
77+
; CHECK-VSX: vcmpequw v[[REG1:[0-9]+]], v4, v5
78+
; CHECK-VSX: xxsel v2, v3, v2, v[[REG1]]
79+
; CHECK-VSX: blr
80+
81+
; CHECK-NOVSX-LABLE: test5
82+
; CHECK-NOVSX: vcmpequw v[[REG1:[0-9]+]], v4, v5
83+
; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]]
84+
; CHECK-NOVSX: blr
85+
86+
define <2 x i64> @test6(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i64> %d) {
87+
entry:
88+
%m = icmp eq <2 x i64> %c, %d
89+
%v = select <2 x i1> %m, <2 x i64> %a, <2 x i64> %b
90+
ret <2 x i64> %v
91+
}
92+
; CHECK-VSX-LABLE: test6
93+
; CHECK-VSX: vcmpequd v[[REG1:[0-9]+]], v4, v5
94+
; CHECK-VSX: xxsel v2, v3, v2, v[[REG1]]
95+
; CHECK-VSX: blr
96+
97+
; CHECK-NOVSX-LABLE: test6
98+
; CHECK-NOVSX: vcmpequd v[[REG1:[0-9]+]], v4, v5
99+
; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]]
100+
; CHECK-NOVSX: blr

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