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pr-feedback: annotation fix & cleanups
Signed-off-by: Nathan Gauër <[email protected]>
1 parent 3baefde commit 6ab5f43

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3 files changed

+151
-101
lines changed

3 files changed

+151
-101
lines changed
Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,36 @@
1+
; RUN: %if spirv-tools %{ spirv-as %s -o - | spirv-val - %}
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; RUN: spirv-sim --function=a --wave=1 --expects=2 -i %s
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; RUN: spirv-sim --function=b --wave=1 --expects=1 -i %s
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OpCapability Shader
5+
OpMemoryModel Logical GLSL450
6+
OpEntryPoint GLCompute %main "main"
7+
OpExecutionMode %main LocalSize 1 1 1
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OpSource HLSL 670
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OpName %a "a"
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OpName %b "b"
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OpName %main "main"
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%int = OpTypeInt 32 1
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%s1 = OpTypeStruct %int %int %int
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%s2 = OpTypeStruct %s1
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%int_1 = OpConstant %int 1
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%int_2 = OpConstant %int 2
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%s1_1_2 = OpConstantComposite %s1 %int_1 %int_2 %int_1
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%s2_s1 = OpConstantComposite %s2 %s1_1_2
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%void = OpTypeVoid
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%main_type = OpTypeFunction %void
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%simple_type = OpTypeFunction %int
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%main = OpFunction %void None %main_type
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%entry = OpLabel
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OpReturn
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OpFunctionEnd
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%a = OpFunction %int None %simple_type
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%1 = OpLabel
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%2 = OpCompositeExtract %int %s1_1_2 1
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OpReturnValue %2
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OpFunctionEnd
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%b = OpFunction %int None %simple_type
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%3 = OpLabel
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%4 = OpCompositeExtract %int %s2_s1 0 2
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OpReturnValue %4
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OpFunctionEnd
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llvm/utils/spirv-sim/instructions.py

Lines changed: 20 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -1,16 +1,16 @@
1+
from typing import Optional
2+
13
# Base class for an instruction. To implement a basic instruction that doesn't
24
# impact the control-flow, create a new class inheriting from this.
35
class Instruction:
4-
_result: str
6+
# Contains the name of the output register, if any.
7+
_result: Optional[str]
8+
# Contains the instruction opcode.
9+
_opcode: str
10+
# Contains all the instruction operands, except result and opcode.
11+
_operands: list[str]
512

613
def __init__(self, line: str):
7-
# Contains the name of the output register, if any.
8-
self._result: str = None
9-
# Contains the instruction opcode.
10-
self._opcode: str = None
11-
# Contains all the instruction operands, except result and opcode.
12-
self._operands: list[str] = []
13-
1414
self.line = line
1515
tokens = line.split()
1616
if len(tokens) > 1 and tokens[1] == "=":
@@ -38,7 +38,7 @@ def operands(self) -> list[str]:
3838
# Returns the instruction output register. Calling this function is
3939
# only allowed if has_output_register() is true.
4040
def output_register(self) -> str:
41-
assert self.has_output_register()
41+
assert self._result is not None
4242
return self._result
4343

4444
# Returns true if this function has an output register. False otherwise.
@@ -132,20 +132,11 @@ def static_execution(self, lane):
132132
class OpConstantComposite(OpConstant):
133133
def static_execution(self, lane):
134134
result = []
135-
length = self.get_register(self._operands[0])
136135
for op in self._operands[1:]:
137-
result.append(self.get_register(op))
136+
result.append(lane.get_register(op))
138137
lane.set_register(self._result, result)
139138

140139

141-
class OpConstantComposite(OpConstant):
142-
def static_execution(self, vm, state):
143-
output = []
144-
for op in self._operands[1:]:
145-
output.append(state.get_register(op))
146-
state.set_register(self._result, output)
147-
148-
149140
# Control flow instructions
150141
class OpFunctionCall(Instruction):
151142
def _impl(self, module, lane):
@@ -217,7 +208,7 @@ def _impl(self, module, lane):
217208

218209

219210
# Convergence instructions
220-
class _MergeInstruction(Instruction):
211+
class MergeInstruction(Instruction):
221212
def merge_location(self):
222213
return self._operands[0]
223214

@@ -228,11 +219,11 @@ def _impl(self, module, lane):
228219
lane.handle_convergence_header(self)
229220

230221

231-
class OpLoopMerge(_MergeInstruction):
222+
class OpLoopMerge(MergeInstruction):
232223
pass
233224

234225

235-
class OpSelectionMerge(_MergeInstruction):
226+
class OpSelectionMerge(MergeInstruction):
236227
pass
237228

238229

@@ -265,6 +256,13 @@ def _impl(self, module, lane):
265256
output.append(lane.get_register(op))
266257
lane.set_register(self._result, output)
267258

259+
class OpCompositeExtract(Instruction):
260+
def _impl(self, module, lane):
261+
value = lane.get_register(self._operands[1])
262+
output = value
263+
for op in self._operands[2:]:
264+
output = output[int(op)]
265+
lane.set_register(self._result, output)
268266

269267
class OpStore(Instruction):
270268
def _impl(self, module, lane):
@@ -303,13 +301,6 @@ def _impl(self, module, lane):
303301
lane.set_register(self._result, not LHS)
304302

305303

306-
class OpSGreaterThan(Instruction):
307-
def _impl(self, module, lane):
308-
LHS = lane.get_register(self._operands[1])
309-
RHS = lane.get_register(self._operands[2])
310-
lane.set_register(self._result, LHS > RHS)
311-
312-
313304
class _LessThan(Instruction):
314305
def _impl(self, module, lane):
315306
LHS = lane.get_register(self._operands[1])

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