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RISCVSchedule.td
1 parent 13d80b4 commit 6abf5b9Copy full SHA for 6abf5b9
llvm/lib/Target/RISCV/RISCVSchedule.td
@@ -64,7 +64,7 @@ def WriteFCvtI64ToF16 : SchedWrite; // RV64I only
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def WriteFCvtI64ToF32 : SchedWrite; // RV64I only
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def WriteFCvtI64ToF64 : SchedWrite; // RV64I only
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-//Float to integer conversions
+// Float to integer conversions
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def WriteFCvtF16ToI32 : SchedWrite;
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def WriteFCvtF16ToI64 : SchedWrite; // RV64I only
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def WriteFCvtF32ToI32 : SchedWrite;
@@ -80,7 +80,7 @@ def WriteFCvtF32ToF16 : SchedWrite;
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def WriteFCvtF16ToF64 : SchedWrite;
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def WriteFCvtF64ToF16 : SchedWrite;
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-// Zfa found instructions.
+// Zfa fround instructions.
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def WriteFRoundF32 : SchedWrite;
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def WriteFRoundF64 : SchedWrite;
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def WriteFRoundF16 : SchedWrite;
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