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MDevereauMDevereau
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Use svuint8_t for all zn parameters
1 parent cf7335d commit 6b419bb

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7 files changed

+107
-108
lines changed

7 files changed

+107
-108
lines changed

‎clang/include/clang/Basic/arm_sme.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -333,6 +333,6 @@ let TargetGuard = "sme2" in {
333333
// lookup table expand four contiguous registers
334334
//
335335
let TargetGuard = "sme2" in {
336-
def SVLUTI2_LANE_ZT_X4 : Inst<"svluti2_lane_zt_{d}_x4", "4.didi", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x4", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>;
337-
def SVLUTI4_LANE_ZT_X4 : Inst<"svluti4_lane_zt_{d}_x4", "4.didi", "sUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x4", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_1>]>;
336+
def SVLUTI2_LANE_ZT_X4 : Inst<"svluti2_lane_zt_{d}_x4", "4.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x4", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>;
337+
def SVLUTI4_LANE_ZT_X4 : Inst<"svluti4_lane_zt_{d}_x4", "4.di[i", "sUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x4", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_1>]>;
338338
}

‎clang/include/clang/Basic/arm_sve_sme_incl.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -93,6 +93,7 @@
9393
// m: uint32_t
9494
// n: uint64_t
9595

96+
// [: svuint8_t
9697
// t: svint32_t
9798
// z: svuint32_t
9899
// g: svuint64_t

‎clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c

Lines changed: 30 additions & 30 deletions
Large diffs are not rendered by default.

‎clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c

Lines changed: 42 additions & 50 deletions
Large diffs are not rendered by default.

‎clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_imm.cpp

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -27,53 +27,53 @@ void test_ldr_str_zt(const void *const_base, void *base) __arm_streaming_compati
2727
// REQUIRES: aarch64-registered-target
2828
#include <arm_sme_draft_spec_subject_to_change.h>
2929

30-
void test_svluti2_lane_zt_x4(svuint8_t zn_u8, svuint16_t zn_u16, svuint32_t zn_u32, svfloat16_t zn_f16, svbfloat16_t zn_bf16, svfloat32_t zn_f32) __arm_streaming __arm_shared_za __arm_preserves_za {
30+
void test_svluti2_lane_zt_x4(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za {
3131
// Test Reg Offset
32-
svluti2_lane_zt_u8_x4(1, zn_u8, 0); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
32+
svluti2_lane_zt_u8_x4(1, zn, 0); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
3333
// Test index value range
34-
svluti2_lane_zt_u8_x4(0, zn_u8, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
34+
svluti2_lane_zt_u8_x4(0, zn, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
3535
// Test Reg Offset
36-
svluti2_lane_zt_u16_x4(1, zn_u16, 3); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
36+
svluti2_lane_zt_u16_x4(1, zn, 3); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
3737
// Test index value range
38-
svluti2_lane_zt_u16_x4(0, zn_u16, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
38+
svluti2_lane_zt_u16_x4(0, zn, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
3939
// Test Reg Offset
40-
svluti2_lane_zt_u32_x4(1, zn_u32, 3); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
40+
svluti2_lane_zt_u32_x4(1, zn, 3); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
4141
// Test index value range
42-
svluti2_lane_zt_u32_x4(0, zn_u32, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
42+
svluti2_lane_zt_u32_x4(0, zn, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
4343
// Test Reg Offset
44-
svluti2_lane_zt_f16_x4(1, zn_f16, 3); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
44+
svluti2_lane_zt_f16_x4(1, zn, 3); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
4545
// Test index value range
46-
svluti2_lane_zt_f16_x4(0, zn_f16, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
46+
svluti2_lane_zt_f16_x4(0, zn, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
4747
// Test Reg Offset
48-
svluti2_lane_zt_bf16_x4(1, zn_bf16, 3); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
48+
svluti2_lane_zt_bf16_x4(1, zn, 3); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
4949
// Test index value range
50-
svluti2_lane_zt_bf16_x4(0, zn_bf16, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
50+
svluti2_lane_zt_bf16_x4(0, zn, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
5151
// Test Reg Offset
52-
svluti2_lane_zt_f32_x4(1, zn_f32, 3); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
52+
svluti2_lane_zt_f32_x4(1, zn, 3); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
5353
// Test index value range
54-
svluti2_lane_zt_f32_x4(0, zn_f32, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
54+
svluti2_lane_zt_f32_x4(0, zn, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
5555
}
5656

57-
void test_svluti4_lane_zt_x4(svuint8_t zn_u8, svuint16_t zn_u16, svuint32_t zn_u32, svfloat16_t zn_f16, svbfloat16_t zn_bf16, svfloat32_t zn_f32) __arm_streaming __arm_shared_za __arm_preserves_za {
57+
void test_svluti4_lane_zt_x4(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za {
5858
// Test Reg Offset
59-
svluti4_lane_zt_u16_x4(1, zn_u16, 0); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
59+
svluti4_lane_zt_u16_x4(1, zn, 0); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
6060
// Test index value range
61-
svluti4_lane_zt_u16_x4(0, zn_u16, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}}
61+
svluti4_lane_zt_u16_x4(0, zn, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}}
6262
// Test Reg Offset
63-
svluti4_lane_zt_u32_x4(1, zn_u32, 1); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
63+
svluti4_lane_zt_u32_x4(1, zn, 1); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
6464
// Test index value range
65-
svluti4_lane_zt_u32_x4(0, zn_u32, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}}
65+
svluti4_lane_zt_u32_x4(0, zn, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}}
6666
// Test Reg Offset
67-
svluti4_lane_zt_f16_x4(1, zn_f16, 0); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
67+
svluti4_lane_zt_f16_x4(1, zn, 0); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
6868
// Test index value range
69-
svluti4_lane_zt_f16_x4(0, zn_f16, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}}
69+
svluti4_lane_zt_f16_x4(0, zn, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}}
7070
// Test Reg Offset
71-
svluti4_lane_zt_bf16_x4(1, zn_bf16, 0); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
71+
svluti4_lane_zt_bf16_x4(1, zn, 0); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
7272
// Test index value range
73-
svluti4_lane_zt_bf16_x4(0, zn_bf16, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}}
73+
svluti4_lane_zt_bf16_x4(0, zn, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}}
7474
// Test Reg Offset
75-
svluti4_lane_zt_f32_x4(1, zn_f32, 1); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
75+
svluti4_lane_zt_f32_x4(1, zn, 1); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
7676
// Test index value range
77-
svluti4_lane_zt_f32_x4(0, zn_f32, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}}
77+
svluti4_lane_zt_f32_x4(0, zn, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}}
7878
}
7979

‎clang/utils/TableGen/SveEmitter.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -744,6 +744,12 @@ void SVEType::applyModifier(char Mod) {
744744
BFloat = false;
745745
ElementBitwidth = 64;
746746
break;
747+
case '[':
748+
Signed = false;
749+
Float = false;
750+
BFloat = false;
751+
ElementBitwidth = 8;
752+
break;
747753
case 't':
748754
Signed = true;
749755
Float = false;

‎llvm/include/llvm/IR/IntrinsicsAArch64.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3554,11 +3554,11 @@ let TargetPrefix = "aarch64" in {
35543554
//
35553555
def int_aarch64_sme_luti2_lane_zt_x4
35563556
: DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
3557-
[llvm_i32_ty, LLVMMatchType<0>, llvm_i32_ty],
3557+
[llvm_i32_ty, llvm_nxv16i8_ty, llvm_i32_ty],
35583558
[ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>, IntrReadMem]>;
35593559
def int_aarch64_sme_luti4_lane_zt_x4
35603560
: DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
3561-
[llvm_i32_ty, LLVMMatchType<0>, llvm_i32_ty],
3561+
[llvm_i32_ty, llvm_nxv16i8_ty, llvm_i32_ty],
35623562
[ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>, IntrReadMem]>;
35633563
}
35643564

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