@@ -2703,7 +2703,7 @@ bool llvm::isIntS34Immediate(SDNode *N, int64_t &Imm) {
2703
2703
if (!isa<ConstantSDNode>(N))
2704
2704
return false;
2705
2705
2706
- Imm = (int64_t)N->getAsZExtVal ();
2706
+ Imm = (int64_t)cast<ConstantSDNode>(N)->getSExtValue ();
2707
2707
return isInt<34>(Imm);
2708
2708
}
2709
2709
bool llvm::isIntS34Immediate(SDValue Op, int64_t &Imm) {
@@ -2925,7 +2925,7 @@ bool PPCTargetLowering::SelectAddressRegImm34(SDValue N, SDValue &Disp,
2925
2925
if (N.getOpcode() == ISD::ADD) {
2926
2926
if (!isIntS34Immediate(N.getOperand(1), Imm))
2927
2927
return false;
2928
- Disp = DAG.getTargetConstant (Imm, dl, N.getValueType());
2928
+ Disp = DAG.getSignedTargetConstant (Imm, dl, N.getValueType());
2929
2929
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0)))
2930
2930
Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2931
2931
else
@@ -2946,12 +2946,12 @@ bool PPCTargetLowering::SelectAddressRegImm34(SDValue N, SDValue &Disp,
2946
2946
Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2947
2947
else
2948
2948
Base = N.getOperand(0);
2949
- Disp = DAG.getTargetConstant (Imm, dl, N.getValueType());
2949
+ Disp = DAG.getSignedTargetConstant (Imm, dl, N.getValueType());
2950
2950
return true;
2951
2951
}
2952
2952
2953
2953
if (isIntS34Immediate(N, Imm)) { // If the address is a 34-bit const.
2954
- Disp = DAG.getTargetConstant (Imm, dl, N.getValueType());
2954
+ Disp = DAG.getSignedTargetConstant (Imm, dl, N.getValueType());
2955
2955
Base = DAG.getRegister(PPC::ZERO8, N.getValueType());
2956
2956
return true;
2957
2957
}
0 commit comments