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fixup! make sure we PrintFatalError
1 parent 9235b8d commit 6b710d0

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1 file changed

+21
-16
lines changed

1 file changed

+21
-16
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llvm/utils/TableGen/SubtargetEmitter.cpp

Lines changed: 21 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -902,19 +902,21 @@ SubtargetEmitter::FindWriteResources(const CodeGenSchedRW &SchedWrite,
902902
for (Record *WR : ProcModel.WriteResDefs) {
903903
if (!WR->isSubClassOf("WriteRes"))
904904
continue;
905-
if (AliasDef == WR->getValueAsDef("WriteType") ||
906-
SchedWrite.TheDef == WR->getValueAsDef("WriteType")) {
905+
// If there is no AliasDef and we find a match, we can early exit since
906+
// there is no need to verify whether there are resources defined for both
907+
// SchedWrite and its alias.
908+
if (!AliasDef && SchedWrite.TheDef == WR->getValueAsDef("WriteType")) {
907909
ResDef = WR;
908910
break;
909-
}
910-
}
911-
912-
if (ResDef && AliasDef) {
913-
PrintFatalError(ResDef->getLoc(), "Resources are defined for both "
911+
} else if (AliasDef == WR->getValueAsDef("WriteType")) {
912+
if (ResDef) {
913+
PrintFatalError(WR->getLoc(), "Resources are defined for both "
914914
"SchedWrite and its alias on processor " +
915915
ProcModel.ModelName);
916+
}
917+
ResDef = WR;
918+
}
916919
}
917-
918920
// TODO: If ProcModel has a base model (previous generation processor),
919921
// then call FindWriteResources recursively with that model here.
920922
if (!ResDef) {
@@ -959,18 +961,21 @@ Record *SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead,
959961
for (Record *RA : ProcModel.ReadAdvanceDefs) {
960962
if (!RA->isSubClassOf("ReadAdvance"))
961963
continue;
962-
if (AliasDef == RA->getValueAsDef("ReadType") ||
963-
SchedRead.TheDef == RA->getValueAsDef("ReadType")) {
964-
ResDef = RA;
964+
// If there is no AliasDef and we find a match, we can early exit since
965+
// there is no need to verify whether there are resources defined for both
966+
// SchedWrite and its alias.
967+
if (!AliasDef && AliasDef == RA->getValueAsDef("ReadType")) {
968+
ResDef = WR;
965969
break;
966-
}
967-
}
968-
if (ResDef && AliasDef) {
969-
PrintFatalError(ResDef->getLoc(), "Resources are defined for both "
970+
} else if (SchedRead.TheDef == RA->getValueAsDef("ReadType")) {
971+
if (ResDef) {
972+
PrintFatalError(RA->getLoc(), "Resources are defined for both "
970973
"SchedRead and its alias on processor " +
971974
ProcModel.ModelName);
975+
}
976+
ResDef = RA;
977+
}
972978
}
973-
974979
// TODO: If ProcModel has a base model (previous generation processor),
975980
// then call FindReadAdvance recursively with that model here.
976981
if (!ResDef && SchedRead.TheDef->getName() != "ReadDefault") {

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