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[MachineCombiner][Targets] Use Register in TII genAlternativeCodeSequence interface. NFC (#131272)
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11 files changed

+32
-33
lines changed

11 files changed

+32
-33
lines changed

‎llvm/include/llvm/CodeGen/TargetInstrInfo.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1306,7 +1306,7 @@ class TargetInstrInfo : public MCInstrInfo {
13061306
MachineInstr &Root, unsigned Pattern,
13071307
SmallVectorImpl<MachineInstr *> &InsInstrs,
13081308
SmallVectorImpl<MachineInstr *> &DelInstrs,
1309-
DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const;
1309+
DenseMap<Register, unsigned> &InstIdxForVirtReg) const;
13101310

13111311
/// When calculate the latency of the root instruction, accumulate the
13121312
/// latency of the sequence to the root latency.
@@ -1329,7 +1329,7 @@ class TargetInstrInfo : public MCInstrInfo {
13291329
SmallVectorImpl<MachineInstr *> &InsInstrs,
13301330
SmallVectorImpl<MachineInstr *> &DelInstrs,
13311331
ArrayRef<unsigned> OperandIndices,
1332-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
1332+
DenseMap<Register, unsigned> &InstrIdxForVirtReg) const;
13331333

13341334
/// Reassociation of some instructions requires inverse operations (e.g.
13351335
/// (X + A) - Y => (X - Y) + A). This method returns a pair of new opcodes

‎llvm/lib/CodeGen/MachineCombiner.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,7 @@ class MachineCombiner : public MachineFunctionPass {
9191
MachineInstr *getOperandDef(const MachineOperand &MO);
9292
bool isTransientMI(const MachineInstr *MI);
9393
unsigned getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs,
94-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg,
94+
DenseMap<Register, unsigned> &InstrIdxForVirtReg,
9595
MachineTraceMetrics::Trace BlockTrace,
9696
const MachineBasicBlock &MBB);
9797
unsigned getLatency(MachineInstr *Root, MachineInstr *NewRoot,
@@ -100,7 +100,7 @@ class MachineCombiner : public MachineFunctionPass {
100100
MachineTraceMetrics::Trace BlockTrace,
101101
SmallVectorImpl<MachineInstr *> &InsInstrs,
102102
SmallVectorImpl<MachineInstr *> &DelInstrs,
103-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg,
103+
DenseMap<Register, unsigned> &InstrIdxForVirtReg,
104104
unsigned Pattern, bool SlackIsAccurate);
105105
bool reduceRegisterPressure(MachineInstr &Root, MachineBasicBlock *MBB,
106106
SmallVectorImpl<MachineInstr *> &InsInstrs,
@@ -202,7 +202,7 @@ bool MachineCombiner::isTransientMI(const MachineInstr *MI) {
202202
/// \returns Depth of last instruction in \InsInstrs ("NewRoot")
203203
unsigned
204204
MachineCombiner::getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs,
205-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg,
205+
DenseMap<Register, unsigned> &InstrIdxForVirtReg,
206206
MachineTraceMetrics::Trace BlockTrace,
207207
const MachineBasicBlock &MBB) {
208208
SmallVector<unsigned, 16> InstrDepth;
@@ -217,7 +217,7 @@ MachineCombiner::getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs,
217217
continue;
218218
unsigned DepthOp = 0;
219219
unsigned LatencyOp = 0;
220-
DenseMap<unsigned, unsigned>::iterator II =
220+
DenseMap<Register, unsigned>::iterator II =
221221
InstrIdxForVirtReg.find(MO.getReg());
222222
if (II != InstrIdxForVirtReg.end()) {
223223
// Operand is new virtual register not in trace
@@ -353,7 +353,7 @@ bool MachineCombiner::improvesCriticalPathLen(
353353
MachineTraceMetrics::Trace BlockTrace,
354354
SmallVectorImpl<MachineInstr *> &InsInstrs,
355355
SmallVectorImpl<MachineInstr *> &DelInstrs,
356-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg, unsigned Pattern,
356+
DenseMap<Register, unsigned> &InstrIdxForVirtReg, unsigned Pattern,
357357
bool SlackIsAccurate) {
358358
// Get depth and latency of NewRoot and Root.
359359
unsigned NewRootDepth =
@@ -527,7 +527,7 @@ void MachineCombiner::verifyPatternOrder(MachineBasicBlock *MBB,
527527
for (auto P : Patterns) {
528528
SmallVector<MachineInstr *, 16> InsInstrs;
529529
SmallVector<MachineInstr *, 16> DelInstrs;
530-
DenseMap<unsigned, unsigned> InstrIdxForVirtReg;
530+
DenseMap<Register, unsigned> InstrIdxForVirtReg;
531531
TII->genAlternativeCodeSequence(Root, P, InsInstrs, DelInstrs,
532532
InstrIdxForVirtReg);
533533
// Found pattern, but did not generate alternative sequence.
@@ -612,7 +612,7 @@ bool MachineCombiner::combineInstructions(MachineBasicBlock *MBB) {
612612
for (const auto P : Patterns) {
613613
SmallVector<MachineInstr *, 16> InsInstrs;
614614
SmallVector<MachineInstr *, 16> DelInstrs;
615-
DenseMap<unsigned, unsigned> InstrIdxForVirtReg;
615+
DenseMap<Register, unsigned> InstrIdxForVirtReg;
616616
TII->genAlternativeCodeSequence(MI, P, InsInstrs, DelInstrs,
617617
InstrIdxForVirtReg);
618618
// Found pattern, but did not generate alternative sequence.

‎llvm/lib/CodeGen/TargetInstrInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1085,7 +1085,7 @@ void TargetInstrInfo::reassociateOps(
10851085
SmallVectorImpl<MachineInstr *> &InsInstrs,
10861086
SmallVectorImpl<MachineInstr *> &DelInstrs,
10871087
ArrayRef<unsigned> OperandIndices,
1088-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
1088+
DenseMap<Register, unsigned> &InstrIdxForVirtReg) const {
10891089
MachineFunction *MF = Root.getMF();
10901090
MachineRegisterInfo &MRI = MF->getRegInfo();
10911091
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
@@ -1250,7 +1250,7 @@ void TargetInstrInfo::genAlternativeCodeSequence(
12501250
MachineInstr &Root, unsigned Pattern,
12511251
SmallVectorImpl<MachineInstr *> &InsInstrs,
12521252
SmallVectorImpl<MachineInstr *> &DelInstrs,
1253-
DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const {
1253+
DenseMap<Register, unsigned> &InstIdxForVirtReg) const {
12541254
MachineRegisterInfo &MRI = Root.getMF()->getRegInfo();
12551255

12561256
// Select the previous instruction in the sequence based on the input pattern.

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Lines changed: 10 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -7360,7 +7360,7 @@ static MachineInstr *genFusedMultiplyAcc(
73607360
static Register genNeg(MachineFunction &MF, MachineRegisterInfo &MRI,
73617361
const TargetInstrInfo *TII, MachineInstr &Root,
73627362
SmallVectorImpl<MachineInstr *> &InsInstrs,
7363-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg,
7363+
DenseMap<Register, unsigned> &InstrIdxForVirtReg,
73647364
unsigned MnegOpc, const TargetRegisterClass *RC) {
73657365
Register NewVR = MRI.createVirtualRegister(RC);
73667366
MachineInstrBuilder MIB =
@@ -7379,7 +7379,7 @@ static Register genNeg(MachineFunction &MF, MachineRegisterInfo &MRI,
73797379
static MachineInstr *genFusedMultiplyAccNeg(
73807380
MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII,
73817381
MachineInstr &Root, SmallVectorImpl<MachineInstr *> &InsInstrs,
7382-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg, unsigned IdxMulOpd,
7382+
DenseMap<Register, unsigned> &InstrIdxForVirtReg, unsigned IdxMulOpd,
73837383
unsigned MaddOpc, unsigned MnegOpc, const TargetRegisterClass *RC) {
73847384
assert(IdxMulOpd == 1);
73857385

@@ -7406,7 +7406,7 @@ static MachineInstr *genFusedMultiplyIdx(
74067406
static MachineInstr *genFusedMultiplyIdxNeg(
74077407
MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII,
74087408
MachineInstr &Root, SmallVectorImpl<MachineInstr *> &InsInstrs,
7409-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg, unsigned IdxMulOpd,
7409+
DenseMap<Register, unsigned> &InstrIdxForVirtReg, unsigned IdxMulOpd,
74107410
unsigned MaddOpc, unsigned MnegOpc, const TargetRegisterClass *RC) {
74117411
assert(IdxMulOpd == 1);
74127412

@@ -7472,13 +7472,12 @@ static MachineInstr *genMaddR(MachineFunction &MF, MachineRegisterInfo &MRI,
74727472
/// Do the following transformation
74737473
/// A - (B + C) ==> (A - B) - C
74747474
/// A - (B + C) ==> (A - C) - B
7475-
static void
7476-
genSubAdd2SubSub(MachineFunction &MF, MachineRegisterInfo &MRI,
7477-
const TargetInstrInfo *TII, MachineInstr &Root,
7478-
SmallVectorImpl<MachineInstr *> &InsInstrs,
7479-
SmallVectorImpl<MachineInstr *> &DelInstrs,
7480-
unsigned IdxOpd1,
7481-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) {
7475+
static void genSubAdd2SubSub(MachineFunction &MF, MachineRegisterInfo &MRI,
7476+
const TargetInstrInfo *TII, MachineInstr &Root,
7477+
SmallVectorImpl<MachineInstr *> &InsInstrs,
7478+
SmallVectorImpl<MachineInstr *> &DelInstrs,
7479+
unsigned IdxOpd1,
7480+
DenseMap<Register, unsigned> &InstrIdxForVirtReg) {
74827481
assert(IdxOpd1 == 1 || IdxOpd1 == 2);
74837482
unsigned IdxOtherOpd = IdxOpd1 == 1 ? 2 : 1;
74847483
MachineInstr *AddMI = MRI.getUniqueVRegDef(Root.getOperand(2).getReg());
@@ -7531,7 +7530,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
75317530
MachineInstr &Root, unsigned Pattern,
75327531
SmallVectorImpl<MachineInstr *> &InsInstrs,
75337532
SmallVectorImpl<MachineInstr *> &DelInstrs,
7534-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
7533+
DenseMap<Register, unsigned> &InstrIdxForVirtReg) const {
75357534
MachineBasicBlock &MBB = *Root.getParent();
75367535
MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
75377536
MachineFunction &MF = *MBB.getParent();

‎llvm/lib/Target/AArch64/AArch64InstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -454,7 +454,7 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
454454
MachineInstr &Root, unsigned Pattern,
455455
SmallVectorImpl<MachineInstr *> &InsInstrs,
456456
SmallVectorImpl<MachineInstr *> &DelInstrs,
457-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
457+
DenseMap<Register, unsigned> &InstrIdxForVirtReg) const override;
458458
/// AArch64 supports MachineCombiner.
459459
bool useMachineCombiner() const override;
460460

‎llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -767,7 +767,7 @@ void PPCInstrInfo::genAlternativeCodeSequence(
767767
MachineInstr &Root, unsigned Pattern,
768768
SmallVectorImpl<MachineInstr *> &InsInstrs,
769769
SmallVectorImpl<MachineInstr *> &DelInstrs,
770-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
770+
DenseMap<Register, unsigned> &InstrIdxForVirtReg) const {
771771
switch (Pattern) {
772772
case PPCMachineCombinerPattern::REASSOC_XY_AMM_BMM:
773773
case PPCMachineCombinerPattern::REASSOC_XMM_AMM_BMM:
@@ -787,7 +787,7 @@ void PPCInstrInfo::reassociateFMA(
787787
MachineInstr &Root, unsigned Pattern,
788788
SmallVectorImpl<MachineInstr *> &InsInstrs,
789789
SmallVectorImpl<MachineInstr *> &DelInstrs,
790-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
790+
DenseMap<Register, unsigned> &InstrIdxForVirtReg) const {
791791
MachineFunction *MF = Root.getMF();
792792
MachineRegisterInfo &MRI = MF->getRegInfo();
793793
const TargetRegisterInfo *TRI = &getRegisterInfo();

‎llvm/lib/Target/PowerPC/PPCInstrInfo.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -241,7 +241,7 @@ class PPCInstrInfo : public PPCGenInstrInfo {
241241
void reassociateFMA(MachineInstr &Root, unsigned Pattern,
242242
SmallVectorImpl<MachineInstr *> &InsInstrs,
243243
SmallVectorImpl<MachineInstr *> &DelInstrs,
244-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
244+
DenseMap<Register, unsigned> &InstrIdxForVirtReg) const;
245245
Register
246246
generateLoadForNewConst(unsigned Idx, MachineInstr *MI, Type *Ty,
247247
SmallVectorImpl<MachineInstr *> &InsInstrs) const;
@@ -370,7 +370,7 @@ class PPCInstrInfo : public PPCGenInstrInfo {
370370
MachineInstr &Root, unsigned Pattern,
371371
SmallVectorImpl<MachineInstr *> &InsInstrs,
372372
SmallVectorImpl<MachineInstr *> &DelInstrs,
373-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
373+
DenseMap<Register, unsigned> &InstrIdxForVirtReg) const override;
374374

375375
/// Return true when there is potentially a faster code sequence for a fma
376376
/// chain ending in \p Root. All potential patterns are output in the \p

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2376,7 +2376,7 @@ static void
23762376
genShXAddAddShift(MachineInstr &Root, unsigned AddOpIdx,
23772377
SmallVectorImpl<MachineInstr *> &InsInstrs,
23782378
SmallVectorImpl<MachineInstr *> &DelInstrs,
2379-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) {
2379+
DenseMap<Register, unsigned> &InstrIdxForVirtReg) {
23802380
MachineFunction *MF = Root.getMF();
23812381
MachineRegisterInfo &MRI = MF->getRegInfo();
23822382
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
@@ -2435,7 +2435,7 @@ void RISCVInstrInfo::genAlternativeCodeSequence(
24352435
MachineInstr &Root, unsigned Pattern,
24362436
SmallVectorImpl<MachineInstr *> &InsInstrs,
24372437
SmallVectorImpl<MachineInstr *> &DelInstrs,
2438-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
2438+
DenseMap<Register, unsigned> &InstrIdxForVirtReg) const {
24392439
MachineRegisterInfo &MRI = Root.getMF()->getRegInfo();
24402440
switch (Pattern) {
24412441
default:

‎llvm/lib/Target/RISCV/RISCVInstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -274,7 +274,7 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
274274
MachineInstr &Root, unsigned Pattern,
275275
SmallVectorImpl<MachineInstr *> &InsInstrs,
276276
SmallVectorImpl<MachineInstr *> &DelInstrs,
277-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
277+
DenseMap<Register, unsigned> &InstrIdxForVirtReg) const override;
278278

279279
bool hasReassociableOperands(const MachineInstr &Inst,
280280
const MachineBasicBlock *MBB) const override;

‎llvm/lib/Target/X86/X86InstrInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10857,7 +10857,7 @@ static void
1085710857
genAlternativeDpCodeSequence(MachineInstr &Root, const TargetInstrInfo &TII,
1085810858
SmallVectorImpl<MachineInstr *> &InsInstrs,
1085910859
SmallVectorImpl<MachineInstr *> &DelInstrs,
10860-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) {
10860+
DenseMap<Register, unsigned> &InstrIdxForVirtReg) {
1086110861
MachineFunction *MF = Root.getMF();
1086210862
MachineRegisterInfo &RegInfo = MF->getRegInfo();
1086310863

@@ -10947,7 +10947,7 @@ void X86InstrInfo::genAlternativeCodeSequence(
1094710947
MachineInstr &Root, unsigned Pattern,
1094810948
SmallVectorImpl<MachineInstr *> &InsInstrs,
1094910949
SmallVectorImpl<MachineInstr *> &DelInstrs,
10950-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
10950+
DenseMap<Register, unsigned> &InstrIdxForVirtReg) const {
1095110951
switch (Pattern) {
1095210952
default:
1095310953
// Reassociate instructions.

‎llvm/lib/Target/X86/X86InstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -641,7 +641,7 @@ class X86InstrInfo final : public X86GenInstrInfo {
641641
MachineInstr &Root, unsigned Pattern,
642642
SmallVectorImpl<MachineInstr *> &InsInstrs,
643643
SmallVectorImpl<MachineInstr *> &DelInstrs,
644-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
644+
DenseMap<Register, unsigned> &InstrIdxForVirtReg) const override;
645645

646646
/// When calculate the latency of the root instruction, accumulate the
647647
/// latency of the sequence to the root latency.

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