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lcvon007lcvon007
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[mi-sched] Suppress register pressure with i64. (#88256)
Machine scheduler will suppress register pressure when the scheduling window is too small, but now it doesn't consider i64 register type, and this MR extends it into i64 register type, so architecture like RISCV64 that only supports i64 interger register will have the same behavior like RISCV32.
1 parent 7177dc2 commit 6b80e2f

14 files changed

+255
-366
lines changed

‎llvm/lib/CodeGen/MachineScheduler.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3281,14 +3281,16 @@ void GenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
32813281

32823282
// Avoid setting up the register pressure tracker for small regions to save
32833283
// compile time. As a rough heuristic, only track pressure when the number of
3284-
// schedulable instructions exceeds half the integer register file.
3284+
// schedulable instructions exceeds half the allocatable integer register file
3285+
// that is the largest legal integer regiser type.
32853286
RegionPolicy.ShouldTrackPressure = true;
3286-
for (unsigned VT = MVT::i32; VT > (unsigned)MVT::i1; --VT) {
3287+
for (unsigned VT = MVT::i64; VT > (unsigned)MVT::i1; --VT) {
32873288
MVT::SimpleValueType LegalIntVT = (MVT::SimpleValueType)VT;
32883289
if (TLI->isTypeLegal(LegalIntVT)) {
32893290
unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs(
32903291
TLI->getRegClassFor(LegalIntVT));
32913292
RegionPolicy.ShouldTrackPressure = NumRegionInstrs > (NIntRegs / 2);
3293+
break;
32923294
}
32933295
}
32943296

‎llvm/test/CodeGen/LoongArch/atomicrmw-uinc-udec-wrap.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -4,12 +4,12 @@
44
define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) {
55
; LA64-LABEL: atomicrmw_uinc_wrap_i8:
66
; LA64: # %bb.0:
7-
; LA64-NEXT: slli.d $a2, $a0, 3
7+
; LA64-NEXT: slli.d $a4, $a0, 3
88
; LA64-NEXT: bstrins.d $a0, $zero, 1, 0
9-
; LA64-NEXT: ori $a3, $zero, 255
10-
; LA64-NEXT: sll.w $a4, $a3, $a2
9+
; LA64-NEXT: andi $a2, $a4, 24
10+
; LA64-NEXT: ori $a5, $zero, 255
1111
; LA64-NEXT: ld.w $a3, $a0, 0
12-
; LA64-NEXT: andi $a2, $a2, 24
12+
; LA64-NEXT: sll.w $a4, $a5, $a4
1313
; LA64-NEXT: nor $a4, $a4, $zero
1414
; LA64-NEXT: andi $a1, $a1, 255
1515
; LA64-NEXT: .p2align 4, , 16
@@ -54,13 +54,13 @@ define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) {
5454
define i16 @atomicrmw_uinc_wrap_i16(ptr %ptr, i16 %val) {
5555
; LA64-LABEL: atomicrmw_uinc_wrap_i16:
5656
; LA64: # %bb.0:
57-
; LA64-NEXT: slli.d $a2, $a0, 3
57+
; LA64-NEXT: slli.d $a4, $a0, 3
5858
; LA64-NEXT: bstrins.d $a0, $zero, 1, 0
59+
; LA64-NEXT: andi $a2, $a4, 24
5960
; LA64-NEXT: lu12i.w $a3, 15
60-
; LA64-NEXT: ori $a3, $a3, 4095
61-
; LA64-NEXT: sll.w $a4, $a3, $a2
61+
; LA64-NEXT: ori $a5, $a3, 4095
6262
; LA64-NEXT: ld.w $a3, $a0, 0
63-
; LA64-NEXT: andi $a2, $a2, 24
63+
; LA64-NEXT: sll.w $a4, $a5, $a4
6464
; LA64-NEXT: nor $a4, $a4, $zero
6565
; LA64-NEXT: bstrpick.d $a1, $a1, 15, 0
6666
; LA64-NEXT: .p2align 4, , 16

‎llvm/test/CodeGen/LoongArch/vector-fp-imm.ll

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -124,10 +124,10 @@ define void @test_f2(ptr %P, ptr %S) nounwind {
124124
; LA64F: # %bb.0:
125125
; LA64F-NEXT: fld.s $fa0, $a0, 4
126126
; LA64F-NEXT: fld.s $fa1, $a0, 0
127-
; LA64F-NEXT: pcalau12i $a0, %pc_hi20(.LCPI1_0)
128-
; LA64F-NEXT: addi.d $a0, $a0, %pc_lo12(.LCPI1_0)
129-
; LA64F-NEXT: fld.s $fa2, $a0, 0
130127
; LA64F-NEXT: addi.w $a0, $zero, 1
128+
; LA64F-NEXT: pcalau12i $a2, %pc_hi20(.LCPI1_0)
129+
; LA64F-NEXT: addi.d $a2, $a2, %pc_lo12(.LCPI1_0)
130+
; LA64F-NEXT: fld.s $fa2, $a2, 0
131131
; LA64F-NEXT: movgr2fr.w $fa3, $a0
132132
; LA64F-NEXT: ffint.s.w $fa3, $fa3
133133
; LA64F-NEXT: fadd.s $fa1, $fa1, $fa3
@@ -140,10 +140,10 @@ define void @test_f2(ptr %P, ptr %S) nounwind {
140140
; LA64D: # %bb.0:
141141
; LA64D-NEXT: fld.s $fa0, $a0, 4
142142
; LA64D-NEXT: fld.s $fa1, $a0, 0
143-
; LA64D-NEXT: pcalau12i $a0, %pc_hi20(.LCPI1_0)
144-
; LA64D-NEXT: addi.d $a0, $a0, %pc_lo12(.LCPI1_0)
145-
; LA64D-NEXT: fld.s $fa2, $a0, 0
146143
; LA64D-NEXT: addi.w $a0, $zero, 1
144+
; LA64D-NEXT: pcalau12i $a2, %pc_hi20(.LCPI1_0)
145+
; LA64D-NEXT: addi.d $a2, $a2, %pc_lo12(.LCPI1_0)
146+
; LA64D-NEXT: fld.s $fa2, $a2, 0
147147
; LA64D-NEXT: movgr2fr.w $fa3, $a0
148148
; LA64D-NEXT: ffint.s.w $fa3, $fa3
149149
; LA64D-NEXT: fadd.s $fa1, $fa1, $fa3
@@ -527,10 +527,10 @@ define void @test_d2(ptr %P, ptr %S) nounwind {
527527
; LA64D: # %bb.0:
528528
; LA64D-NEXT: fld.d $fa0, $a0, 8
529529
; LA64D-NEXT: fld.d $fa1, $a0, 0
530-
; LA64D-NEXT: pcalau12i $a0, %pc_hi20(.LCPI4_0)
531-
; LA64D-NEXT: addi.d $a0, $a0, %pc_lo12(.LCPI4_0)
532-
; LA64D-NEXT: fld.d $fa2, $a0, 0
533530
; LA64D-NEXT: addi.d $a0, $zero, 1
531+
; LA64D-NEXT: pcalau12i $a2, %pc_hi20(.LCPI4_0)
532+
; LA64D-NEXT: addi.d $a2, $a2, %pc_lo12(.LCPI4_0)
533+
; LA64D-NEXT: fld.d $fa2, $a2, 0
534534
; LA64D-NEXT: movgr2fr.d $fa3, $a0
535535
; LA64D-NEXT: ffint.d.l $fa3, $fa3
536536
; LA64D-NEXT: fadd.d $fa1, $fa1, $fa3

‎llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -127,11 +127,11 @@ define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) {
127127
; RV64IA-LABEL: atomicrmw_uinc_wrap_i8:
128128
; RV64IA: # %bb.0:
129129
; RV64IA-NEXT: andi a2, a0, -4
130-
; RV64IA-NEXT: slli a0, a0, 3
131-
; RV64IA-NEXT: li a3, 255
132-
; RV64IA-NEXT: sllw a4, a3, a0
130+
; RV64IA-NEXT: slli a4, a0, 3
131+
; RV64IA-NEXT: andi a0, a4, 24
132+
; RV64IA-NEXT: li a5, 255
133133
; RV64IA-NEXT: lw a3, 0(a2)
134-
; RV64IA-NEXT: andi a0, a0, 24
134+
; RV64IA-NEXT: sllw a4, a5, a4
135135
; RV64IA-NEXT: not a4, a4
136136
; RV64IA-NEXT: andi a1, a1, 255
137137
; RV64IA-NEXT: .LBB0_1: # %atomicrmw.start

‎llvm/test/CodeGen/RISCV/bfloat-convert.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -84,12 +84,12 @@ define i16 @fcvt_si_bf16_sat(bfloat %a) nounwind {
8484
; CHECK64ZFBFMIN: # %bb.0: # %start
8585
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
8686
; CHECK64ZFBFMIN-NEXT: feq.s a0, fa5, fa5
87+
; CHECK64ZFBFMIN-NEXT: neg a0, a0
8788
; CHECK64ZFBFMIN-NEXT: lui a1, %hi(.LCPI1_0)
8889
; CHECK64ZFBFMIN-NEXT: flw fa4, %lo(.LCPI1_0)(a1)
8990
; CHECK64ZFBFMIN-NEXT: lui a1, 815104
9091
; CHECK64ZFBFMIN-NEXT: fmv.w.x fa3, a1
9192
; CHECK64ZFBFMIN-NEXT: fmax.s fa5, fa5, fa3
92-
; CHECK64ZFBFMIN-NEXT: neg a0, a0
9393
; CHECK64ZFBFMIN-NEXT: fmin.s fa5, fa5, fa4
9494
; CHECK64ZFBFMIN-NEXT: fcvt.l.s a1, fa5, rtz
9595
; CHECK64ZFBFMIN-NEXT: and a0, a0, a1
@@ -187,10 +187,10 @@ define i16 @fcvt_ui_bf16_sat(bfloat %a) nounwind {
187187
;
188188
; RV64ID-LABEL: fcvt_ui_bf16_sat:
189189
; RV64ID: # %bb.0: # %start
190-
; RV64ID-NEXT: lui a0, %hi(.LCPI3_0)
191-
; RV64ID-NEXT: flw fa5, %lo(.LCPI3_0)(a0)
192190
; RV64ID-NEXT: fmv.x.w a0, fa0
193191
; RV64ID-NEXT: slli a0, a0, 16
192+
; RV64ID-NEXT: lui a1, %hi(.LCPI3_0)
193+
; RV64ID-NEXT: flw fa5, %lo(.LCPI3_0)(a1)
194194
; RV64ID-NEXT: fmv.w.x fa4, a0
195195
; RV64ID-NEXT: fmv.w.x fa3, zero
196196
; RV64ID-NEXT: fmax.s fa4, fa4, fa3

‎llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -140,11 +140,11 @@ define i64 @caller_large_scalars() nounwind {
140140
; RV64I-NEXT: sd a0, 0(sp)
141141
; RV64I-NEXT: sd zero, 56(sp)
142142
; RV64I-NEXT: sd zero, 48(sp)
143-
; RV64I-NEXT: li a0, 1
144-
; RV64I-NEXT: sd a0, 32(sp)
143+
; RV64I-NEXT: sd zero, 40(sp)
144+
; RV64I-NEXT: li a2, 1
145145
; RV64I-NEXT: addi a0, sp, 32
146146
; RV64I-NEXT: mv a1, sp
147-
; RV64I-NEXT: sd zero, 40(sp)
147+
; RV64I-NEXT: sd a2, 32(sp)
148148
; RV64I-NEXT: call callee_large_scalars
149149
; RV64I-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
150150
; RV64I-NEXT: addi sp, sp, 80

‎llvm/test/CodeGen/RISCV/double-convert.ll

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1651,8 +1651,8 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
16511651
; RV64IFD-NEXT: lui a0, %hi(.LCPI26_1)
16521652
; RV64IFD-NEXT: fld fa4, %lo(.LCPI26_1)(a0)
16531653
; RV64IFD-NEXT: feq.d a0, fa0, fa0
1654-
; RV64IFD-NEXT: fmax.d fa5, fa0, fa5
16551654
; RV64IFD-NEXT: neg a0, a0
1655+
; RV64IFD-NEXT: fmax.d fa5, fa0, fa5
16561656
; RV64IFD-NEXT: fmin.d fa5, fa5, fa4
16571657
; RV64IFD-NEXT: fcvt.l.d a1, fa5, rtz
16581658
; RV64IFD-NEXT: and a0, a0, a1
@@ -1680,12 +1680,12 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
16801680
; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI26_0)(a1)
16811681
; RV64IZFINXZDINX-NEXT: lui a2, %hi(.LCPI26_1)
16821682
; RV64IZFINXZDINX-NEXT: ld a2, %lo(.LCPI26_1)(a2)
1683-
; RV64IZFINXZDINX-NEXT: fmax.d a1, a0, a1
1684-
; RV64IZFINXZDINX-NEXT: feq.d a0, a0, a0
1685-
; RV64IZFINXZDINX-NEXT: neg a0, a0
1686-
; RV64IZFINXZDINX-NEXT: fmin.d a1, a1, a2
1687-
; RV64IZFINXZDINX-NEXT: fcvt.l.d a1, a1, rtz
1688-
; RV64IZFINXZDINX-NEXT: and a0, a0, a1
1683+
; RV64IZFINXZDINX-NEXT: feq.d a3, a0, a0
1684+
; RV64IZFINXZDINX-NEXT: neg a3, a3
1685+
; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, a1
1686+
; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a2
1687+
; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rtz
1688+
; RV64IZFINXZDINX-NEXT: and a0, a3, a0
16891689
; RV64IZFINXZDINX-NEXT: ret
16901690
;
16911691
; RV32I-LABEL: fcvt_w_s_sat_i16:
@@ -2026,8 +2026,8 @@ define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind {
20262026
; RV64IFD-NEXT: lui a0, %hi(.LCPI30_1)
20272027
; RV64IFD-NEXT: fld fa4, %lo(.LCPI30_1)(a0)
20282028
; RV64IFD-NEXT: feq.d a0, fa0, fa0
2029-
; RV64IFD-NEXT: fmax.d fa5, fa0, fa5
20302029
; RV64IFD-NEXT: neg a0, a0
2030+
; RV64IFD-NEXT: fmax.d fa5, fa0, fa5
20312031
; RV64IFD-NEXT: fmin.d fa5, fa5, fa4
20322032
; RV64IFD-NEXT: fcvt.l.d a1, fa5, rtz
20332033
; RV64IFD-NEXT: and a0, a0, a1
@@ -2055,12 +2055,12 @@ define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind {
20552055
; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI30_0)(a1)
20562056
; RV64IZFINXZDINX-NEXT: lui a2, %hi(.LCPI30_1)
20572057
; RV64IZFINXZDINX-NEXT: ld a2, %lo(.LCPI30_1)(a2)
2058-
; RV64IZFINXZDINX-NEXT: fmax.d a1, a0, a1
2059-
; RV64IZFINXZDINX-NEXT: feq.d a0, a0, a0
2060-
; RV64IZFINXZDINX-NEXT: neg a0, a0
2061-
; RV64IZFINXZDINX-NEXT: fmin.d a1, a1, a2
2062-
; RV64IZFINXZDINX-NEXT: fcvt.l.d a1, a1, rtz
2063-
; RV64IZFINXZDINX-NEXT: and a0, a0, a1
2058+
; RV64IZFINXZDINX-NEXT: feq.d a3, a0, a0
2059+
; RV64IZFINXZDINX-NEXT: neg a3, a3
2060+
; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, a1
2061+
; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a2
2062+
; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rtz
2063+
; RV64IZFINXZDINX-NEXT: and a0, a3, a0
20642064
; RV64IZFINXZDINX-NEXT: ret
20652065
;
20662066
; RV32I-LABEL: fcvt_w_s_sat_i8:

‎llvm/test/CodeGen/RISCV/float-convert.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1424,12 +1424,12 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
14241424
; RV64IF-LABEL: fcvt_w_s_sat_i16:
14251425
; RV64IF: # %bb.0: # %start
14261426
; RV64IF-NEXT: feq.s a0, fa0, fa0
1427+
; RV64IF-NEXT: neg a0, a0
14271428
; RV64IF-NEXT: lui a1, %hi(.LCPI24_0)
14281429
; RV64IF-NEXT: flw fa5, %lo(.LCPI24_0)(a1)
14291430
; RV64IF-NEXT: lui a1, 815104
14301431
; RV64IF-NEXT: fmv.w.x fa4, a1
14311432
; RV64IF-NEXT: fmax.s fa4, fa0, fa4
1432-
; RV64IF-NEXT: neg a0, a0
14331433
; RV64IF-NEXT: fmin.s fa5, fa4, fa5
14341434
; RV64IF-NEXT: fcvt.l.s a1, fa5, rtz
14351435
; RV64IF-NEXT: and a0, a0, a1
@@ -1450,15 +1450,15 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
14501450
;
14511451
; RV64IZFINX-LABEL: fcvt_w_s_sat_i16:
14521452
; RV64IZFINX: # %bb.0: # %start
1453-
; RV64IZFINX-NEXT: lui a1, 815104
1453+
; RV64IZFINX-NEXT: feq.s a1, a0, a0
14541454
; RV64IZFINX-NEXT: lui a2, %hi(.LCPI24_0)
14551455
; RV64IZFINX-NEXT: lw a2, %lo(.LCPI24_0)(a2)
1456-
; RV64IZFINX-NEXT: fmax.s a1, a0, a1
1457-
; RV64IZFINX-NEXT: feq.s a0, a0, a0
1458-
; RV64IZFINX-NEXT: neg a0, a0
1459-
; RV64IZFINX-NEXT: fmin.s a1, a1, a2
1460-
; RV64IZFINX-NEXT: fcvt.l.s a1, a1, rtz
1461-
; RV64IZFINX-NEXT: and a0, a0, a1
1456+
; RV64IZFINX-NEXT: neg a1, a1
1457+
; RV64IZFINX-NEXT: lui a3, 815104
1458+
; RV64IZFINX-NEXT: fmax.s a0, a0, a3
1459+
; RV64IZFINX-NEXT: fmin.s a0, a0, a2
1460+
; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz
1461+
; RV64IZFINX-NEXT: and a0, a1, a0
14621462
; RV64IZFINX-NEXT: ret
14631463
;
14641464
; RV32I-LABEL: fcvt_w_s_sat_i16:

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