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[AMDGPU][NFC] Rename the clamp modifier definition to follow the prevailing convention. (#94353)
Allows to simplify the definition itself. Part of <#62629>.
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-52
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8 files changed

+55
-52
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‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 15 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -126,7 +126,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
126126
ImmTyCPol,
127127
ImmTyTFE,
128128
ImmTyD16,
129-
ImmTyClampSI,
129+
ImmTyClamp,
130130
ImmTyOModSI,
131131
ImmTySDWADstSel,
132132
ImmTySDWASrc0Sel,
@@ -1084,7 +1084,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
10841084
case ImmTyTFE: OS << "TFE"; break;
10851085
case ImmTyD16: OS << "D16"; break;
10861086
case ImmTyFORMAT: OS << "FORMAT"; break;
1087-
case ImmTyClampSI: OS << "ClampSI"; break;
1087+
case ImmTyClamp: OS << "Clamp"; break;
10881088
case ImmTyOModSI: OS << "OModSI"; break;
10891089
case ImmTyDPP8: OS << "DPP8"; break;
10901090
case ImmTyDppCtrl: OS << "DppCtrl"; break;
@@ -5062,8 +5062,8 @@ bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
50625062
return false;
50635063
}
50645064
if (!validateIntClampSupported(Inst)) {
5065-
Error(getImmLoc(AMDGPUOperand::ImmTyClampSI, Operands),
5066-
"integer clamping is not supported on this GPU");
5065+
Error(getImmLoc(AMDGPUOperand::ImmTyClamp, Operands),
5066+
"integer clamping is not supported on this GPU");
50675067
return false;
50685068
}
50695069
if (!validateOpSel(Inst)) {
@@ -8512,7 +8512,7 @@ void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands)
85128512

85138513
if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))
85148514
addOptionalImmOperand(Inst, Operands, OptionalIdx,
8515-
AMDGPUOperand::ImmTyClampSI);
8515+
AMDGPUOperand::ImmTyClamp);
85168516

85178517
if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))
85188518
addOptionalImmOperand(Inst, Operands, OptionalIdx,
@@ -8541,7 +8541,7 @@ void AMDGPUAsmParser::cvtVINTERP(MCInst &Inst, const OperandVector &Operands)
85418541
}
85428542
}
85438543

8544-
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);
8544+
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClamp);
85458545

85468546
int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);
85478547
if (OpSelIdx != -1)
@@ -8611,7 +8611,7 @@ void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands,
86118611

86128612
if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))
86138613
addOptionalImmOperand(Inst, Operands, OptionalIdx,
8614-
AMDGPUOperand::ImmTyClampSI);
8614+
AMDGPUOperand::ImmTyClamp);
86158615

86168616
if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))
86178617
addOptionalImmOperand(Inst, Operands, OptionalIdx,
@@ -8788,7 +8788,7 @@ void AMDGPUAsmParser::cvtSWMMAC(MCInst &Inst, const OperandVector &Operands) {
87888788
AMDGPUOperand::ImmTyIndexKey16bit);
87898789

87908790
if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))
8791-
addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyClampSI);
8791+
addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyClamp);
87928792

87938793
cvtVOP3P(Inst, Operands, OptIdx);
87948794
}
@@ -9211,7 +9211,8 @@ void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,
92119211
AMDGPUOperand::ImmTyByteSel);
92129212

92139213
if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))
9214-
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);
9214+
addOptionalImmOperand(Inst, Operands, OptionalIdx,
9215+
AMDGPUOperand::ImmTyClamp);
92159216

92169217
if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))
92179218
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);
@@ -9443,7 +9444,7 @@ void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
94439444
case SIInstrFlags::VOP1:
94449445
if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))
94459446
addOptionalImmOperand(Inst, Operands, OptionalIdx,
9446-
AMDGPUOperand::ImmTyClampSI, 0);
9447+
AMDGPUOperand::ImmTyClamp, 0);
94479448

94489449
if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))
94499450
addOptionalImmOperand(Inst, Operands, OptionalIdx,
@@ -9462,7 +9463,8 @@ void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
94629463
break;
94639464

94649465
case SIInstrFlags::VOP2:
9465-
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);
9466+
addOptionalImmOperand(Inst, Operands, OptionalIdx,
9467+
AMDGPUOperand::ImmTyClamp, 0);
94669468

94679469
if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::omod))
94689470
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI, 0);
@@ -9475,7 +9477,8 @@ void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
94759477

94769478
case SIInstrFlags::VOPC:
94779479
if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::clamp))
9478-
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);
9480+
addOptionalImmOperand(Inst, Operands, OptionalIdx,
9481+
AMDGPUOperand::ImmTyClamp, 0);
94799482
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD);
94809483
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc1Sel, SdwaSel::DWORD);
94819484
break;

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1071,8 +1071,8 @@ def omod0 : DefaultOperand<omod, 0>;
10711071
// We need to make the cases with a default of 0 distinct from no
10721072
// default to help deal with some cases where the operand appears
10731073
// before a mandatory operand.
1074-
def clampmod : NamedBitOperand<"clamp", "ClampSI">;
1075-
def clampmod0 : DefaultOperand<clampmod, 0>;
1074+
def Clamp : NamedBitOperand<"clamp">;
1075+
def Clamp0 : DefaultOperand<Clamp, 0>;
10761076
def highmod : NamedBitOperand<"high", "High">;
10771077

10781078
def CPol : CustomOperand<i32, 1>;
@@ -1714,14 +1714,14 @@ class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
17141714
// VOP1 with modifiers
17151715
!if(HasOMod,
17161716
(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1717-
clampmod0:$clamp, omod0:$omod),
1717+
Clamp0:$clamp, omod0:$omod),
17181718
!if (HasClamp,
1719-
(ins Src0Mod:$src0_modifiers, Src0RC:$src0, clampmod0:$clamp),
1719+
(ins Src0Mod:$src0_modifiers, Src0RC:$src0, Clamp0:$clamp),
17201720
(ins Src0Mod:$src0_modifiers, Src0RC:$src0)))
17211721
/* else */,
17221722
// VOP1 without modifiers
17231723
!if (HasClamp,
1724-
(ins Src0RC:$src0, clampmod0:$clamp),
1724+
(ins Src0RC:$src0, Clamp0:$clamp),
17251725
(ins Src0RC:$src0))
17261726
/* endif */ ),
17271727
!if (!eq(NumSrcArgs, 2),
@@ -1730,14 +1730,14 @@ class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
17301730
!if(HasOMod,
17311731
(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
17321732
Src1Mod:$src1_modifiers, Src1RC:$src1,
1733-
clampmod0:$clamp, omod0:$omod),
1733+
Clamp0:$clamp, omod0:$omod),
17341734
!con((ins Src0Mod:$src0_modifiers, Src0RC:$src0,
17351735
Src1Mod:$src1_modifiers, Src1RC:$src1),
1736-
!if(HasClamp, (ins clampmod0:$clamp), (ins))))
1736+
!if(HasClamp, (ins Clamp0:$clamp), (ins))))
17371737
/* else */,
17381738
// VOP2 without modifiers
17391739
!if (HasClamp,
1740-
(ins Src0RC:$src0, Src1RC:$src1, clampmod0:$clamp),
1740+
(ins Src0RC:$src0, Src1RC:$src1, Clamp0:$clamp),
17411741
(ins Src0RC:$src0, Src1RC:$src1))
17421742

17431743
/* endif */ )
@@ -1749,31 +1749,31 @@ class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
17491749
(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
17501750
Src1Mod:$src1_modifiers, Src1RC:$src1,
17511751
Src2Mod:$src2_modifiers, Src2RC:$src2,
1752-
clampmod0:$clamp, omod0:$omod),
1752+
Clamp0:$clamp, omod0:$omod),
17531753
!if (HasClamp,
17541754
(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
17551755
Src1Mod:$src1_modifiers, Src1RC:$src1,
17561756
Src2Mod:$src2_modifiers, Src2RC:$src2,
1757-
clampmod0:$clamp),
1757+
Clamp0:$clamp),
17581758
(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
17591759
Src1Mod:$src1_modifiers, Src1RC:$src1,
17601760
Src2Mod:$src2_modifiers, Src2RC:$src2))),
17611761
// VOP3 with modifiers except src2
17621762
!if (HasOMod,
17631763
(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
17641764
Src1Mod:$src1_modifiers, Src1RC:$src1,
1765-
Src2RC:$src2, clampmod0:$clamp, omod0:$omod),
1765+
Src2RC:$src2, Clamp0:$clamp, omod0:$omod),
17661766
!if (HasClamp,
17671767
(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
17681768
Src1Mod:$src1_modifiers, Src1RC:$src1,
1769-
Src2RC:$src2, clampmod0:$clamp),
1769+
Src2RC:$src2, Clamp0:$clamp),
17701770
(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
17711771
Src1Mod:$src1_modifiers, Src1RC:$src1,
17721772
Src2RC:$src2))))
17731773
/* else */,
17741774
// VOP3 without modifiers
17751775
!if (HasClamp,
1776-
(ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2, clampmod0:$clamp),
1776+
(ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2, Clamp0:$clamp),
17771777
(ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2))
17781778
/* endif */ ))));
17791779
}
@@ -1919,32 +1919,32 @@ class getInsSDWA <RegisterOperand Src0RC, RegisterOperand Src1RC, int NumSrcArgs
19191919
!if(!not(HasSDWAOMod),
19201920
// VOP1_SDWA without omod
19211921
(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1922-
clampmod:$clamp,
1922+
Clamp:$clamp,
19231923
dst_sel:$dst_sel, dst_unused:$dst_unused,
19241924
src0_sel:$src0_sel),
19251925
// VOP1_SDWA with omod
19261926
(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1927-
clampmod:$clamp, omod:$omod,
1927+
Clamp:$clamp, omod:$omod,
19281928
dst_sel:$dst_sel, dst_unused:$dst_unused,
19291929
src0_sel:$src0_sel)),
19301930
!if(!eq(NumSrcArgs, 2),
19311931
!if(!eq(DstVT.Size, 1),
19321932
// VOPC_SDWA
19331933
(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
19341934
Src1Mod:$src1_modifiers, Src1RC:$src1,
1935-
clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel),
1935+
Clamp:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel),
19361936
// VOP2_SDWA
19371937
!if(!not(HasSDWAOMod),
19381938
// VOP2_SDWA without omod
19391939
(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
19401940
Src1Mod:$src1_modifiers, Src1RC:$src1,
1941-
clampmod:$clamp,
1941+
Clamp:$clamp,
19421942
dst_sel:$dst_sel, dst_unused:$dst_unused,
19431943
src0_sel:$src0_sel, src1_sel:$src1_sel),
19441944
// VOP2_SDWA with omod
19451945
(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
19461946
Src1Mod:$src1_modifiers, Src1RC:$src1,
1947-
clampmod:$clamp, omod:$omod,
1947+
Clamp:$clamp, omod:$omod,
19481948
dst_sel:$dst_sel, dst_unused:$dst_unused,
19491949
src0_sel:$src0_sel, src1_sel:$src1_sel))),
19501950
(ins)/* endif */)));

‎llvm/lib/Target/AMDGPU/VINTERPInstructions.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -77,7 +77,7 @@ def VOP3_VINTERP_F32 : VOPProfile<[f32, f32, f32, f32]> {
7777
let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
7878
Src1Mod:$src1_modifiers, VRegSrc_32:$src1,
7979
Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
80-
clampmod:$clamp,
80+
Clamp:$clamp,
8181
WaitEXP:$waitexp);
8282

8383
let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$waitexp";
@@ -95,7 +95,7 @@ class VOP3_VINTERP_F16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> {
9595
let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
9696
Src1Mod:$src1_modifiers, VRegSrc_32:$src1,
9797
Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
98-
clampmod:$clamp, op_sel0:$op_sel,
98+
Clamp:$clamp, op_sel0:$op_sel,
9999
WaitEXP:$waitexp);
100100

101101
let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$op_sel$waitexp";

‎llvm/lib/Target/AMDGPU/VOP1Instructions.td

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -178,8 +178,8 @@ multiclass VOP1Inst_t16<string opName, VOPProfile P,
178178
class VOPProfileI2F<ValueType dstVt, ValueType srcVt> :
179179
VOPProfile<[dstVt, srcVt, untyped, untyped]> {
180180

181-
let Ins64 = (ins Src0RC64:$src0, clampmod:$clamp, omod:$omod);
182-
let InsVOP3Base = (ins Src0VOP3DPP:$src0, clampmod:$clamp, omod:$omod);
181+
let Ins64 = (ins Src0RC64:$src0, Clamp:$clamp, omod:$omod);
182+
let InsVOP3Base = (ins Src0VOP3DPP:$src0, Clamp:$clamp, omod:$omod);
183183
let AsmVOP3Base = "$vdst, $src0$clamp$omod";
184184

185185
let HasModifiers = 0;
@@ -189,8 +189,8 @@ class VOPProfileI2F<ValueType dstVt, ValueType srcVt> :
189189
class VOPProfileI2F_True16<ValueType dstVt, ValueType srcVt> :
190190
VOPProfile_Fake16<VOPProfile<[dstVt, srcVt, untyped, untyped]>> {
191191

192-
let Ins64 = (ins Src0RC64:$src0, clampmod:$clamp, omod:$omod);
193-
let InsVOP3Base = (ins Src0VOP3DPP:$src0, clampmod:$clamp, omod:$omod);
192+
let Ins64 = (ins Src0RC64:$src0, Clamp:$clamp, omod:$omod);
193+
let InsVOP3Base = (ins Src0VOP3DPP:$src0, Clamp:$clamp, omod:$omod);
194194
let AsmVOP3Base = "$vdst, $src0$clamp$omod";
195195

196196
let HasModifiers = 0;
@@ -379,7 +379,7 @@ class VOP_MOVREL<RegisterOperand Src1RC> : VOPProfile<[untyped, i32, untyped, un
379379

380380
let OutsSDWA = (outs Src0RC32:$vdst);
381381
let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
382-
clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused,
382+
Clamp:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused,
383383
src0_sel:$src0_sel);
384384
let AsmSDWA9 = getAsmSDWA9<1, 0, 1>.ret;
385385

@@ -563,7 +563,7 @@ class VOPProfile_Base_CVT_F32_F8<ValueType vt> : VOPProfileI2F <vt, i32> {
563563
let HasExt = 1;
564564
let DstRCSDWA = getVALUDstForVT<vt>.ret;
565565
let InsSDWA = (ins Bin32SDWAInputMods:$src0_modifiers, Src0SDWA:$src0,
566-
clampmod:$clamp, omod:$omod, src0_sel:$src0_sel);
566+
Clamp:$clamp, omod:$omod, src0_sel:$src0_sel);
567567
let AsmSDWA = "$vdst, $src0_modifiers$clamp$omod $src0_sel"; // No dst_sel
568568
let AsmSDWA9 = AsmSDWA;
569569
let EmitDstSel = 0;

‎llvm/lib/Target/AMDGPU/VOP2Instructions.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -350,7 +350,7 @@ class VOP2eInstAlias <VOP2_Pseudo ps, Instruction inst, string opnd = ""> :
350350
class VOP2e64InstAlias <VOP3_Pseudo ps, Instruction inst> :
351351
InstAlias <ps.OpName#" "#ps.Pfl.Asm64,
352352
(inst ps.Pfl.DstRC:$vdst, VOPDstS64orS32:$sdst,
353-
ps.Pfl.Src0RC32:$src0, ps.Pfl.Src1RC32:$src1, clampmod:$clamp),
353+
ps.Pfl.Src0RC32:$src0, ps.Pfl.Src1RC32:$src1, Clamp:$clamp),
354354
1, inst.AsmVariantName>,
355355
PredicateControl;
356356

@@ -451,7 +451,7 @@ class VOP_MAC <ValueType vt0, ValueType vt1=vt0> : VOPProfile <[vt0, vt1, vt1, v
451451
let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
452452
Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
453453
getVregSrcForVT<Src2VT>.ret:$src2, // stub argument
454-
clampmod:$clamp, omod:$omod,
454+
Clamp:$clamp, omod:$omod,
455455
dst_sel:$dst_sel, dst_unused:$dst_unused,
456456
src0_sel:$src0_sel, src1_sel:$src1_sel);
457457
let Asm32 = getAsm32<1, 2, vt0>.ret;
@@ -586,7 +586,7 @@ def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], /*EnableClamp=*/1>
586586

587587
let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
588588
Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
589-
clampmod:$clamp,
589+
Clamp:$clamp,
590590
dst_sel:$dst_sel, dst_unused:$dst_unused,
591591
src0_sel:$src0_sel, src1_sel:$src1_sel);
592592

@@ -637,7 +637,7 @@ class VOP2e_SGPR<list<ValueType> ArgVT> : VOPProfile<ArgVT> {
637637
let HasSrc1FloatMods = 1;
638638
let InsSDWA = (ins FP32SDWAInputMods:$src0_modifiers, SDWASrc_f32:$src0,
639639
FP32SDWAInputMods:$src1_modifiers, SDWASrc_f32:$src1,
640-
clampmod:$clamp,
640+
Clamp:$clamp,
641641
dst_sel:$dst_sel, dst_unused:$dst_unused,
642642
src0_sel:$src0_sel, src1_sel:$src1_sel);
643643

‎llvm/lib/Target/AMDGPU/VOP3Instructions.td

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -62,15 +62,15 @@ def VOP3_INTERP : VOPProfile<[f32, f32, i32, untyped]> {
6262
let Src0Mod = FPVRegInputMods;
6363
let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
6464
InterpAttr:$attr, InterpAttrChan:$attrchan,
65-
clampmod0:$clamp, omod0:$omod);
65+
Clamp0:$clamp, omod0:$omod);
6666

6767
let Asm64 = "$vdst, $src0_modifiers, $attr$attrchan$clamp$omod";
6868
}
6969

7070
def VOP3_INTERP_MOV : VOPProfile<[f32, i32, i32, untyped]> {
7171
let Ins64 = (ins InterpSlot:$src0,
7272
InterpAttr:$attr, InterpAttrChan:$attrchan,
73-
clampmod0:$clamp, omod0:$omod);
73+
Clamp0:$clamp, omod0:$omod);
7474

7575
let Asm64 = "$vdst, $src0, $attr$attrchan$clamp$omod";
7676

@@ -92,15 +92,15 @@ class getInterp16Ins <bit HasSrc2, bit HasOMod,
9292
(ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
9393
InterpAttr:$attr, InterpAttrChan:$attrchan,
9494
Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
95-
highmod:$high, clampmod0:$clamp, omod0:$omod),
95+
highmod:$high, Clamp0:$clamp, omod0:$omod),
9696
(ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
9797
InterpAttr:$attr, InterpAttrChan:$attrchan,
9898
Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
99-
highmod:$high, clampmod0:$clamp)
99+
highmod:$high, Clamp0:$clamp)
100100
),
101101
(ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
102102
InterpAttr:$attr, InterpAttrChan:$attrchan,
103-
highmod:$high, clampmod0:$clamp, omod0:$omod)
103+
highmod:$high, Clamp0:$clamp, omod0:$omod)
104104
);
105105
}
106106

‎llvm/lib/Target/AMDGPU/VOP3PInstructions.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -38,13 +38,13 @@ class VOP3P_Mix_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR,
3838
FPVRegInputMods:$src1_modifiers, VRegSrc_32:$src1,
3939
FP16InputMods:$src2_modifiers, VCSrc_f16:$src2);
4040

41-
// FIXME: clampmod0 misbehaves with the non-default vdst_in
41+
// FIXME: Clamp0 misbehaves with the non-default vdst_in
4242
// following it. For now workaround this by requiring clamp
4343
// in tied patterns. This should use undef_tied_input, but it
4444
// seems underdeveloped and doesn't apply the right register
4545
// class constraints.
46-
dag mods = !con(!if(UseTiedOutput, (ins clampmod:$clamp, VGPR_32:$vdst_in),
47-
(ins clampmod0:$clamp)),
46+
dag mods = !con(!if(UseTiedOutput, (ins Clamp:$clamp, VGPR_32:$vdst_in),
47+
(ins Clamp0:$clamp)),
4848
(ins op_sel0:$op_sel, op_sel_hi0:$op_sel_hi));
4949
// We use Ins64 because that is the one which populates InOperandList
5050
// due to the logic in class VOP3_Pseudo
@@ -1055,7 +1055,7 @@ class VOP3PWMMA_Profile<list<ValueType> ArgTy, bit _IsSWMMAC, int _IndexType,
10551055
dag IndexKey = !cond(!eq(IndexType, 0) : (ins),
10561056
!eq(IndexType, 8) : (ins IndexKey8bit:$index_key_8bit),
10571057
!eq(IndexType, 16): (ins IndexKey16bit:$index_key_16bit));
1058-
dag Clamp = !if(IsIU, (ins clampmod0:$clamp), (ins));
1058+
dag Clamp = !if(IsIU, (ins Clamp0:$clamp), (ins));
10591059
dag Neg = !cond(!and(NegLoAny, NegHiAny) : (ins neg_lo0:$neg_lo, neg_hi0:$neg_hi),
10601060
!and(NegLoAny, !not(NegHiAny)) : (ins neg_lo0:$neg_lo),
10611061
!and(!not(NegLoAny), !not(NegHiAny)) : (ins));

‎llvm/lib/Target/AMDGPU/VOPCInstructions.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -779,7 +779,7 @@ class VOPC_Class_Profile<list<SchedReadWrite> sched, ValueType src0VT, ValueType
779779

780780
let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
781781
Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
782-
clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel);
782+
Clamp:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel);
783783

784784
let AsmSDWA = " vcc, $src0_modifiers, $src1_modifiers$clamp $src0_sel $src1_sel";
785785
let HasSrc1Mods = 0;

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