@@ -13898,18 +13898,20 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
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// Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
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// bits, it is already ready.
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return Op;
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- } else if (OpBits < DestBits) {
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+ }
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+
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+ if (OpBits < DestBits) {
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// Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
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// bits, just sext from i32.
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return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Op);
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- } else {
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- // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
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- // bits, just truncate to i32.
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- SDNodeFlags Flags;
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- Flags.setNoSignedWrap(true);
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- Flags.setNoUnsignedWrap(N0->getFlags().hasNoUnsignedWrap());
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- return DAG.getNode(ISD::TRUNCATE, DL, VT, Op, Flags);
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}
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+
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+ // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
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+ // bits, just truncate to i32.
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+ SDNodeFlags Flags;
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+ Flags.setNoSignedWrap(true);
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+ Flags.setNoUnsignedWrap(N0->getFlags().hasNoUnsignedWrap());
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+ return DAG.getNode(ISD::TRUNCATE, DL, VT, Op, Flags);
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}
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// fold (sext (truncate x)) -> (sextinreg x).
@@ -14187,19 +14189,21 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
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// Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
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// bits, it is already ready.
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return Op;
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- } else if (OpBits < DestBits) {
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+ }
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+
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+ if (OpBits < DestBits) {
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// Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
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// bits, just sext from i32.
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// FIXME: This can probably be ZERO_EXTEND nneg?
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return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Op);
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- } else {
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- // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
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- // bits, just truncate to i32.
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- SDNodeFlags Flags;
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- Flags.setNoSignedWrap(true);
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- Flags.setNoUnsignedWrap(true);
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- return DAG.getNode(ISD::TRUNCATE, DL, VT, Op, Flags);
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}
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+
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+ // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
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+ // bits, just truncate to i32.
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+ SDNodeFlags Flags;
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+ Flags.setNoSignedWrap(true);
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+ Flags.setNoUnsignedWrap(true);
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+ return DAG.getNode(ISD::TRUNCATE, DL, VT, Op, Flags);
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}
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}
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