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Reformat fp16 patterns to character limit
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llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -6097,12 +6097,14 @@ def : Pat<(f64 (uint_to_fp (i64 (vector_extract (v2i64 FPR128:$Rn), (i64 0))))),
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// fp16: integer extraction from vector must be at least 32-bits to be legal.
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// Actual extraction result is then an in-reg sign-extension of lower 16-bits.
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let Predicates = [HasNEONandIsStreamingSafe, HasFullFP16] in {
6100-
def : Pat<(f16 (sint_to_fp (i32 (sext_inreg (i32 (vector_extract (v8i16 FPR128:$Rn), (i64 0))), i16)))),
6101-
(SCVTFv1i16 (f16 (EXTRACT_SUBREG (v8i16 FPR128:$Rn), hsub)))>;
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def : Pat<(f16 (sint_to_fp (i32 (sext_inreg (i32 (vector_extract
6101+
(v8i16 FPR128:$Rn), (i64 0))), i16)))),
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(SCVTFv1i16 (f16 (EXTRACT_SUBREG (v8i16 FPR128:$Rn), hsub)))>;
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// unsigned 32-bit extracted element is truncated to 16-bits using AND
6104-
def : Pat<(f16 (uint_to_fp (i32 (and (i32 (vector_extract (v8i16 FPR128:$Rn), (i64 0))), (i32 65535))))),
6105-
(UCVTFv1i16 (f16 (EXTRACT_SUBREG (v8i16 FPR128:$Rn), hsub)))>;
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def : Pat<(f16 (uint_to_fp (i32 (and (i32 (vector_extract
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(v8i16 FPR128:$Rn), (i64 0))), (i32 65535))))),
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(UCVTFv1i16 (f16 (EXTRACT_SUBREG (v8i16 FPR128:$Rn), hsub)))>;
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}
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// If an integer is about to be converted to a floating point value,

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