[CodeGen] Fix forward scan in MachineBasicBlock::computeRegisterLiveness.

The scan was incorrectly skipping the first instruction, so a register
could appear to be dead when it was actually live. This eventually leads
to a machine verifier failure and miscompile in arm-ldst-opt.

Differential Revision: https://reviews.llvm.org/D54491

llvm-svn: 346821

Author: Eli Friedman

llvm/lib/CodeGen/MachineBasicBlock.cpp

@@ -1380,24 +1380,21 @@ MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI,
 
   // Try searching forwards from Before, looking for reads or defs.
   const_iterator I(Before);
-  // If this is the last insn in the block, don't search forwards.
-  if (I != end()) {
-    for (++I; I != end() && N > 0; ++I) {
-      if (I->isDebugInstr())
-        continue;
+  for (; I != end() && N > 0; ++I) {
+    if (I->isDebugInstr())
+      continue;
 
-      --N;
+    --N;
 
-      MachineOperandIteratorBase::PhysRegInfo Info =
-          ConstMIOperands(*I).analyzePhysReg(Reg, TRI);
+    MachineOperandIteratorBase::PhysRegInfo Info =
+        ConstMIOperands(*I).analyzePhysReg(Reg, TRI);
 
-      // Register is live when we read it here.
-      if (Info.Read)
-        return LQR_Live;
-      // Register is dead if we can fully overwrite or clobber it here.
-      if (Info.FullyDefined || Info.Clobbered)
-        return LQR_Dead;
-    }
+    // Register is live when we read it here.
+    if (Info.Read)
+      return LQR_Live;
+    // Register is dead if we can fully overwrite or clobber it here.
+    if (Info.FullyDefined || Info.Clobbered)
+      return LQR_Dead;
   }
 
   // If we reached the end, it is safe to clobber Reg at the end of a block of

llvm/test/CodeGen/ARM/load_store_opt_clobber_cpsr.mir

@@ -0,0 +1,33 @@
+# RUN: llc -mtriple=thumbv6m--eabi -verify-machineinstrs -run-pass=arm-ldst-opt %s -o - | FileCheck %s
+
+# Make sure bb.0 isn't transformed: it would incorrectly clobber CPSR.
+#
+# Make sure bb.1 is transformed, so the test doesn't accidentally break.
+
+# CHECK-LABEL: bb.0:
+# CHECK: renamable $r0 = tLDRi renamable $r4, 0, 14, $noreg :: (load 4)
+# CHECK: renamable $r1 = tLDRi renamable $r4, 1, 14, $noreg :: (load 4)
+
+# CHECK-LABEL: bb.1:
+# CHECK: $r4 = tLDMIA_UPD $r4, 14, $noreg, def $r0, def $r1
+# CHECK: $r4, dead $cpsr = tSUBi8 $r4, 8, 14, $noreg
+
+name: foo
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $r2, $r4
+    renamable $r0 = tLDRi renamable $r2, 4, 14, $noreg :: (load 4)
+    dead renamable $r0, $cpsr = tADDi3 killed renamable $r0, 1, 14, $noreg
+    renamable $r0 = tLDRi renamable $r4, 0, 14, $noreg :: (load 4)
+    renamable $r1 = tLDRi renamable $r4, 1, 14, $noreg :: (load 4)
+    tBcc %bb.1, 0, killed $cpsr
+  bb.1:
+    liveins: $r2, $r4
+    renamable $r0 = tLDRi renamable $r2, 4, 14, $noreg :: (load 4)
+    dead renamable $r0, $cpsr = tADDi3 killed renamable $r0, 1, 14, $noreg
+    renamable $r0 = tLDRi renamable $r4, 0, 14, $noreg :: (load 4)
+    renamable $r1 = tLDRi renamable $r4, 1, 14, $noreg :: (load 4)
+  bb.2:
+    liveins: $r4
+    TRAP