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[SimplifyCFG] Fix bugs and Address reviews
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+161
-45
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5 files changed

+161
-45
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llvm/lib/Transforms/Utils/SimplifyCFG.cpp

Lines changed: 56 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -1618,27 +1618,39 @@ bool SimplifyCFGOpt::hoistCommonCodeFromSuccessors(BasicBlock *BB,
16181618

16191619
auto *TI = BB->getTerminator();
16201620

1621-
SmallVector<BasicBlock *> SuccessorBlocks;
1622-
for (auto *Succ : successors(BB))
1623-
SuccessorBlocks.push_back(Succ);
1621+
SmallVector<BasicBlock *, 8> SuccessorBBs;
1622+
for (auto *Succ : successors(BB)) {
1623+
BasicBlock::iterator SuccItr = Succ->begin();
1624+
// If we find an unreachable instruction at the beginning of a basic block,
1625+
// we can still hoist instructions from the rest of the basic blocks.
1626+
if (isa<UnreachableInst>(*SuccItr))
1627+
continue;
1628+
SuccessorBBs.push_back(Succ);
1629+
}
16241630

1625-
// Sort successor blocks based on the number of instructions.
1626-
// This is because we always want to iterate over instructions
1627-
// of the smallest block.
1628-
llvm::stable_sort(SuccessorBlocks, [](BasicBlock *BB1, BasicBlock *BB2) {
1629-
return BB1->sizeWithoutDebug() < BB2->sizeWithoutDebug();
1630-
});
1631+
// Find the smallest BB because we always want to iterate over instructions
1632+
// of the smallest Successor.
1633+
auto *SmallestBB = *std::min_element(SuccessorBBs.begin(), SuccessorBBs.end(),
1634+
[](BasicBlock *BB1, BasicBlock *BB2) {
1635+
return BB1->size() < BB2->size();
1636+
});
1637+
std::iter_swap(
1638+
SuccessorBBs.begin(),
1639+
std::find(SuccessorBBs.begin(), SuccessorBBs.end(), SmallestBB));
16311640

16321641
// The second of pair is a SkipFlags bitmask.
16331642
using SuccIterPair = std::pair<BasicBlock::iterator, unsigned>;
16341643
SmallVector<SuccIterPair, 8> SuccIterPairs;
1635-
for (auto *Succ : SuccessorBlocks) {
1644+
for (auto *Succ : SuccessorBBs) {
16361645
BasicBlock::iterator SuccItr = Succ->begin();
16371646
if (isa<PHINode>(*SuccItr))
16381647
return false;
16391648
SuccIterPairs.push_back(SuccIterPair(SuccItr, 0));
16401649
}
16411650

1651+
if (SuccIterPairs.size() < 2)
1652+
return false;
1653+
16421654
// Check if only hoisting terminators is allowed. This does not add new
16431655
// instructions to the hoist location.
16441656
if (EqTermsOnly) {
@@ -1656,14 +1668,6 @@ bool SimplifyCFGOpt::hoistCommonCodeFromSuccessors(BasicBlock *BB,
16561668
// many instructions we skip, serving as a compilation time control as well as
16571669
// preventing excessive increase of life ranges.
16581670
unsigned NumSkipped = 0;
1659-
// If we find an unreachable instruction at the beginning of a basic block, we
1660-
// can still hoist instructions from the rest of the basic blocks.
1661-
if (SuccIterPairs.size() > 2) {
1662-
erase_if(SuccIterPairs,
1663-
[](const auto &Pair) { return isa<UnreachableInst>(Pair.first); });
1664-
if (SuccIterPairs.size() < 2)
1665-
return false;
1666-
}
16671671

16681672
bool Changed = false;
16691673
auto *SuccIterPairBegin = SuccIterPairs.begin();
@@ -1704,7 +1708,7 @@ bool SimplifyCFGOpt::hoistCommonCodeFromSuccessors(BasicBlock *BB,
17041708
Instruction *I2 = map[getHash(I1)].first;
17051709
// We might face with same hash values for different instructions.
17061710
// If that happens, ignore the instruction.
1707-
if (!I2 || !I1->isIdenticalTo(I2)) {
1711+
if (!I2 || !I1->isIdenticalToWhenDefined(I2)) {
17081712
HasIdenticalInst = false;
17091713
break;
17101714
}
@@ -1720,7 +1724,7 @@ bool SimplifyCFGOpt::hoistCommonCodeFromSuccessors(BasicBlock *BB,
17201724
SuccIterPair.second |= skippedInstrFlags(I);
17211725
}
17221726
}
1723-
NumSkipped++;
1727+
++NumSkipped;
17241728
if (I1->isTerminator())
17251729
return Changed;
17261730
++BB1ItrPair.first;
@@ -1810,13 +1814,38 @@ bool SimplifyCFGOpt::hoistCommonCodeFromSuccessors(BasicBlock *BB,
18101814
for (auto &map : OtherSuccessorsHash) {
18111815
Instruction *I2 = map[getHash(I1)].first;
18121816
assert(I2 != I1);
1813-
if (!I2->use_empty())
1817+
// Update hashcode of all instructions using I2
1818+
if (!I2->use_empty()) {
1819+
SmallVector<llvm::hash_code, 8> PrevHashCodes;
1820+
SmallVector<llvm::Instruction *, 8> PrevUsers;
1821+
// Once the uses of I1 are replaced, the hash value computed for
1822+
// those users are not valid anymore so we gather users and then
1823+
// recompute the hash codes for them. We need to do this only for
1824+
// the instructions located in the same block as I2 because we
1825+
// initially only hashed those instructions.
1826+
for (auto *user : I2->users()) {
1827+
if (auto *I = dyn_cast<Instruction>(user)) {
1828+
if (I->getParent() != I2->getParent())
1829+
continue;
1830+
PrevHashCodes.push_back(getHash(I));
1831+
PrevUsers.push_back(I);
1832+
}
1833+
}
18141834
I2->replaceAllUsesWith(I1);
1835+
unsigned index = 0;
1836+
for (auto &PrevHash : PrevHashCodes) {
1837+
auto NewHash = getHash(PrevUsers[index]);
1838+
std::swap(map[NewHash], map[PrevHash]);
1839+
map.erase(PrevHash);
1840+
index++;
1841+
}
1842+
}
18151843
I1->andIRFlags(I2);
18161844
combineMetadataForCSE(I1, I2, true);
18171845
// I1 and I2 are being combined into a single instruction. Its debug
18181846
// location is the merged locations of the original instructions.
18191847
I1->applyMergedLocation(I1->getDebugLoc(), I2->getDebugLoc());
1848+
map.erase(getHash(I1));
18201849
I2->eraseFromParent();
18211850
}
18221851
}
@@ -1832,10 +1861,11 @@ bool SimplifyCFGOpt::hoistCommonCodeFromSuccessors(BasicBlock *BB,
18321861
// We are about to skip over a pair of non-identical instructions. Record
18331862
// if any have characteristics that would prevent reordering instructions
18341863
// across them.
1864+
BB1ItrPair.first++;
18351865
SkipFlagsBB1 |= skippedInstrFlags(I1);
18361866
if (SameLevelHoist) {
18371867
for (auto &SuccIterPair : OtherSuccIterPairRange) { // update flags
1838-
Instruction *I = &*SuccIterPair.first;
1868+
Instruction *I = &*SuccIterPair.first++;
18391869
SuccIterPair.second |= skippedInstrFlags(I);
18401870
}
18411871
}
@@ -1952,16 +1982,20 @@ bool SimplifyCFGOpt::hoistSuccIdenticalTerminatorToSwitchOrIf(
19521982
}
19531983
}
19541984
}
1985+
19551986
SmallVector<DominatorTree::UpdateType, 4> Updates;
1987+
19561988
// Update any PHI nodes in our new successors.
19571989
for (BasicBlock *Succ : successors(BB1)) {
19581990
AddPredecessorToBlock(Succ, TIParent, BB1);
19591991
if (DTU)
19601992
Updates.push_back({DominatorTree::Insert, TIParent, Succ});
19611993
}
1994+
19621995
if (DTU)
19631996
for (BasicBlock *Succ : successors(TI))
19641997
Updates.push_back({DominatorTree::Delete, TIParent, Succ});
1998+
19651999
EraseTerminatorAndDCECond(TI);
19662000
if (DTU)
19672001
DTU->applyUpdates(Updates);
@@ -3713,7 +3747,6 @@ static bool FoldTwoEntryPHINode(PHINode *PN, const TargetTransformInfo &TTI,
37133747
// Change the PHI node into a select instruction.
37143748
Value *TrueVal = PN->getIncomingValueForBlock(IfTrue);
37153749
Value *FalseVal = PN->getIncomingValueForBlock(IfFalse);
3716-
37173750
Value *Sel = Builder.CreateSelect(IfCond, TrueVal, FalseVal, "", DomBI);
37183751
PN->replaceAllUsesWith(Sel);
37193752
Sel->takeName(PN);

llvm/test/CodeGen/ARM/aes-erratum-fix.ll

Lines changed: 7 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -314,16 +314,15 @@ define arm_aapcs_vfpcc void @aese_set8_cond_via_ptr(i1 zeroext %0, ptr %1, <16 x
314314
; CHECK-FIX-LABEL: aese_set8_cond_via_ptr:
315315
; CHECK-FIX: @ %bb.0:
316316
; CHECK-FIX-NEXT: vorr q0, q0, q0
317+
; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2]
317318
; CHECK-FIX-NEXT: cmp r0, #0
318319
; CHECK-FIX-NEXT: beq .LBB12_2
319320
; CHECK-FIX-NEXT: @ %bb.1:
320-
; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2]
321321
; CHECK-FIX-NEXT: vld1.8 {d16[0]}, [r1]
322322
; CHECK-FIX-NEXT: cmp r0, #0
323323
; CHECK-FIX-NEXT: bne .LBB12_3
324324
; CHECK-FIX-NEXT: b .LBB12_4
325325
; CHECK-FIX-NEXT: .LBB12_2:
326-
; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2]
327326
; CHECK-FIX-NEXT: cmp r0, #0
328327
; CHECK-FIX-NEXT: beq .LBB12_4
329328
; CHECK-FIX-NEXT: .LBB12_3:
@@ -3205,23 +3204,18 @@ define arm_aapcs_vfpcc void @aesd_set64_via_val(i64 %0, <16 x i8> %1, ptr %2) no
32053204
define arm_aapcs_vfpcc void @aesd_set64_cond_via_ptr(i1 zeroext %0, ptr %1, <16 x i8> %2, ptr %3) nounwind {
32063205
; CHECK-FIX-NOSCHED-LABEL: aesd_set64_cond_via_ptr:
32073206
; CHECK-FIX-NOSCHED: @ %bb.0:
3208-
; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0
3209-
; CHECK-FIX-NOSCHED-NEXT: beq .LBB76_2
3210-
; CHECK-FIX-NOSCHED-NEXT: @ %bb.1:
3211-
; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r2]
3212-
; CHECK-FIX-NOSCHED-NEXT: vldr d16, [r1]
3213-
; CHECK-FIX-NOSCHED-NEXT: b .LBB76_3
3214-
; CHECK-FIX-NOSCHED-NEXT: .LBB76_2:
32153207
; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r2]
3216-
; CHECK-FIX-NOSCHED-NEXT: .LBB76_3:
3208+
; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0
3209+
; CHECK-FIX-NOSCHED-NEXT: vldrne d16, [r1]
3210+
; CHECK-FIX-NOSCHED-NEXT: vorr q8, q8, q8
32173211
; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0
32183212
; CHECK-FIX-NOSCHED-NEXT: vldrne d0, [r1]
32193213
; CHECK-FIX-NOSCHED-NEXT: vorr q0, q0, q0
32203214
; CHECK-FIX-NOSCHED-NEXT: aesd.8 q8, q0
32213215
; CHECK-FIX-NOSCHED-NEXT: aesimc.8 q8, q8
32223216
; CHECK-FIX-NOSCHED-NEXT: vst1.64 {d16, d17}, [r2]
32233217
; CHECK-FIX-NOSCHED-NEXT: bx lr
3224-
;
3218+
32253219
; CHECK-CORTEX-FIX-LABEL: aesd_set64_cond_via_ptr:
32263220
; CHECK-CORTEX-FIX: @ %bb.0:
32273221
; CHECK-CORTEX-FIX-NEXT: cmp r0, #0
@@ -4096,19 +4090,15 @@ define arm_aapcs_vfpcc void @aesd_setf32_cond_via_ptr(i1 zeroext %0, ptr %1, <16
40964090
; CHECK-FIX-LABEL: aesd_setf32_cond_via_ptr:
40974091
; CHECK-FIX: @ %bb.0:
40984092
; CHECK-FIX-NEXT: vorr q0, q0, q0
4093+
; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2]
40994094
; CHECK-FIX-NEXT: cmp r0, #0
41004095
; CHECK-FIX-NEXT: beq .LBB88_2
41014096
; CHECK-FIX-NEXT: @ %bb.1:
4102-
; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2]
41034097
; CHECK-FIX-NEXT: vld1.32 {d16[0]}, [r1:32]
4104-
; CHECK-FIX-NEXT: cmp r0, #0
4105-
; CHECK-FIX-NEXT: bne .LBB88_3
4106-
; CHECK-FIX-NEXT: b .LBB88_4
41074098
; CHECK-FIX-NEXT: .LBB88_2:
4108-
; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2]
41094099
; CHECK-FIX-NEXT: cmp r0, #0
41104100
; CHECK-FIX-NEXT: beq .LBB88_4
4111-
; CHECK-FIX-NEXT: .LBB88_3:
4101+
; CHECK-FIX-NEXT: @ %bb.3:
41124102
; CHECK-FIX-NEXT: vld1.32 {d0[0]}, [r1:32]
41134103
; CHECK-FIX-NEXT: .LBB88_4:
41144104
; CHECK-FIX-NEXT: aesd.8 q8, q0

llvm/test/CodeGen/Thumb2/mve-memtp-branch.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11,8 +11,8 @@ define i32 @a(i8 zeroext %b, ptr nocapture readonly %c, ptr nocapture readonly %
1111
; CHECK: @ %bb.0: @ %entry
1212
; CHECK-NEXT: .save {r4, r5, r7, lr}
1313
; CHECK-NEXT: push {r4, r5, r7, lr}
14-
; CHECK-NEXT: cmp r0, #2
15-
; CHECK-NEXT: bls.w .LBB0_12
14+
; CHECK-NEXT: cmp r0, #3
15+
; CHECK-NEXT: blo.w .LBB0_12
1616
; CHECK-NEXT: @ %bb.1: @ %for.body.us.preheader
1717
; CHECK-NEXT: movw r5, :lower16:arr_183
1818
; CHECK-NEXT: movs r3, #0
Lines changed: 87 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,87 @@
1+
; opt -passes='default<O3>' -S --mtriple=aarch64-linux-gnu --mcpu=a64fx < %s | FileCheck %s
2+
3+
; Hoist identical instructions from successor blocks even if
4+
; they are not located at the same level. This could help generate
5+
; more compact vectorized code.
6+
; More info can be found at https://github.com/llvm/llvm-project/issues/68395.
7+
8+
9+
define void @hoist_then_vectorize(ptr %a, ptr %b, ptr %c, ptr %d, i32 %N){
10+
; CHECK-LABEL: @hoist_then_vectorize(
11+
; CHECK-NEXT: iter.check:
12+
; CHECK-NEXT: [[VSCALE:%.*]] = tail call i64 @llvm.vscale.i64()
13+
; CHECK-NEXT: [[SHIFT:%.*]] = shl i64 [[VSCALE:%.*]], 1
14+
; CHECK-NEXT: [[MIN_ITR:%.*]] = icmp ugt i64 [[SHIFT:%.*]], 20
15+
; CHECK-NEXT: br i1 [[MIN_ITR:%.*]], label [[FOR_BODY_PREHEADER:%.*]], label [[VECTOR_MAIN_LOOP_ITR_CHECK:%.*]]
16+
; CHECK: vector.main.loop.iter.check:
17+
; CHECK-NEXT: [[VSCALE2:%.*]] = tail call i64 @llvm.vscale.i64()
18+
; CHECK-NEXT: [[SHIFT2:%.*]] = shl i64 [[VSCALE2:%.*]], 2
19+
; CHECK-NEXT: [[MIN_ITR2:%.*]] = icmp ugt i64 [[SHIFT2:%.*]], 20
20+
; CHECK-NEXT: br i1 [[MIN_ITR2:%.*]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]]
21+
; CHECK: vector.ph:
22+
; CHECK-NEXT: [[VSCALE3:%.*]] = tail call i64 @llvm.vscale.i64()
23+
; CHECK-NEXT: [[SHIFT3:%.*]] = shl i64 [[VSCALE3:%.*]], 2
24+
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 20, [[SHIFT3:%.*]]
25+
; CHECK-NEXT: [[N_VEC:%.*]] = sub nuw nsw i64 20, [[N_MOD_VF:%.*]]
26+
; CHECK-NEXT: [[VSCALE4:%.*]] = tail call i64 @llvm.vscale.i64()
27+
; CHECK-NEXT: [[SHIFT4:%.*]] = shl i64 [[VSCALE4:%.*]], 2
28+
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
29+
; CHECK: vector.body:
30+
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY:%.*]] ]
31+
; CHECK-NEXT: [[GEP_D:%.*]] = getelementptr inbounds i32, ptr [[D:%.*]], i64 [[INDEX:%.*]]
32+
; CHECK-NEXT: [[LOAD_D:%.*]] = load <vscale x 4 x i32>, ptr [[GEP_D:%.*]], align 4
33+
; CHECK-NEXT: [[MASK1:%.*]] = icmp slt <vscale x 4 x i32> [[LOAD_D:%.*]], zeroinitializer
34+
; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[INDEX:%.*]]
35+
; CHECK-NEXT: [[LOAD_A:%.*]] = load <vscale x 4 x i32>, ptr [[GEP_A:%.*]], align 4
36+
; CHECK-NEXT: [[MASK2:%.*]] = icmp eq <vscale x 4 x i32> [[LOAD_A:%.*]], zeroinitializer
37+
; CHECK-NEXT: [[SEL1:%.*]] = select <vscale x 4 x i1> [[MASK2:%.*]], <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 2, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer), <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 3, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
38+
; CHECK-NEXT: [[SEL2:%.*]] = select <vscale x 4 x i1> [[MASK1:%.*]], <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 1, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer), <vscale x 4 x i32> [[SEL1:%.*]]
39+
; CHECK-NEXT: [[ADD:%.*]] = add <vscale x 4 x i32> [[LOAD_A:%.*]], [[SEL2:%.*]]
40+
; CHECK-NEXT: store <vscale x 4 x i32> [[ADD:%.*]], ptr [[GEP_A:%.*]], align 4
41+
; CHECK-NEXT: [[INDEX_NEXT:%.*]] = add nuw i64 [[INDEX:%.*]], [[SHIFT4:%.*]]
42+
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp eq i64 [[INDEX_NEXT:%.*]], [[N_VEC:%.*]]
43+
; CHECK-NEXT: br i1 [[LOOP_COND:%.*]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY:%.*]]
44+
45+
entry:
46+
br label %for.body
47+
48+
for.cond.cleanup: ; preds = %for.inc
49+
ret void
50+
51+
for.body: ; preds = %entry, %for.inc
52+
%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.inc ]
53+
%arrayidx = getelementptr inbounds i32, ptr %d, i64 %indvars.iv
54+
%ldr_d = load i32, ptr %arrayidx, align 4
55+
%cmp1 = icmp slt i32 %ldr_d, 0
56+
br i1 %cmp1, label %if.then, label %if.else
57+
58+
if.then: ; preds = %for.body
59+
%arrayidx3 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv
60+
%ldr_a = load i32, ptr %arrayidx3, align 4
61+
%add33 = add i32 %ldr_a, 1
62+
store i32 %add33, ptr %arrayidx3, align 4
63+
br label %for.inc
64+
65+
if.else: ; preds = %for.body
66+
%cmp7 = icmp eq i32 %ldr_d, 0
67+
br i1 %cmp7, label %if.then9, label %if.else15
68+
69+
if.then9: ; preds = %if.else
70+
%arrayidx11 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv
71+
%ldr_a2 = load i32, ptr %arrayidx11, align 4
72+
%add1334 = add i32 %ldr_a2, 2
73+
store i32 %add1334, ptr %arrayidx11, align 4
74+
br label %for.inc
75+
76+
if.else15: ; preds = %if.else
77+
%arrayidx112 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv
78+
%ldr_a3 = load i32, ptr %arrayidx112, align 4
79+
%add1935 = add i32 %ldr_a3, 3
80+
store i32 %add1935, ptr %arrayidx112, align 4
81+
br label %for.inc
82+
83+
for.inc: ; preds = %if.then, %if.else15, %if.then9
84+
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
85+
%exitcond.not = icmp eq i64 %indvars.iv.next, 20
86+
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
87+
}

llvm/test/Transforms/SimplifyCFG/dont-hoist-deoptimize.ll

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3,21 +3,25 @@
33
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128-ni:1-p2:32:8:8:32-ni:2"
44
target triple = "x86_64-unknown-linux-gnu"
55

6+
; SimplifyCFG hoists %tmp and %tmp2 but after skipping %tmp3, we reach to the skipping threshold and
7+
; bail out, not hoisting %tmp4.
8+
69
declare void @llvm.experimental.deoptimize.isVoid(...) #0
710

811
define void @widget(i1 %arg) {
912
; CHECK-LABEL: @widget(
1013
; CHECK-NEXT: bb:
1114
; CHECK-NEXT: [[TMP:%.*]] = trunc i64 5 to i32
15+
; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 0 to i32
1216
; CHECK-NEXT: br i1 [[ARG:%.*]], label [[BB1:%.*]], label [[BB4:%.*]]
1317
; CHECK: bb1:
14-
; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 0 to i32
1518
; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 0 to i32
19+
; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 2 to i32
1620
; CHECK-NEXT: call void (...) @llvm.experimental.deoptimize.isVoid(i32 13) #[[ATTR0:[0-9]+]] [ "deopt"() ]
1721
; CHECK-NEXT: ret void
1822
; CHECK: bb4:
19-
; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 1 to i32
20-
; CHECK-NEXT: [[TMP7:%.*]] = trunc i64 0 to i32
23+
; CHECK-NEXT: [[TMP7:%.*]] = trunc i64 1 to i32
24+
; CHECK-NEXT: [[TMP8:%.*]] = trunc i64 2 to i32
2125
; CHECK-NEXT: call void (...) @llvm.experimental.deoptimize.isVoid(i32 13) #[[ATTR0]] [ "deopt"() ]
2226
; CHECK-NEXT: ret void
2327
;
@@ -28,13 +32,15 @@ bb1: ; preds = %bb
2832
%tmp = trunc i64 5 to i32
2933
%tmp2 = trunc i64 0 to i32
3034
%tmp3 = trunc i64 0 to i32
35+
%tmp4 = trunc i64 2 to i32
3136
call void (...) @llvm.experimental.deoptimize.isVoid(i32 13) #0 [ "deopt"() ]
3237
ret void
3338

3439
bb4: ; preds = %bb
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%tmp5 = trunc i64 5 to i32
3641
%tmp6 = trunc i64 1 to i32
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%tmp7 = trunc i64 0 to i32
43+
%tmp8 = trunc i64 2 to i32
3844
call void (...) @llvm.experimental.deoptimize.isVoid(i32 13) #0 [ "deopt"() ]
3945
ret void
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}

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