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[RISCV] Simplify some code in lowering vector int<->fp conversions. NFC
Don't call EltVT.getSizeInBits() or SrcEltVT.getSizeInBits() a second time. They are already in EltSize or SrcEltSize variables. Refactor some comparisons to use multiply instead of division.
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llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -3381,10 +3381,10 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
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33823382
bool IsInt2FP = SrcEltVT.isInteger();
33833383
// Widening conversions
3384-
if (EltSize > SrcEltSize && (EltSize / SrcEltSize >= 4)) {
3384+
if (EltSize > (2 * SrcEltSize)) {
33853385
if (IsInt2FP) {
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// Do a regular integer sign/zero extension then convert to float.
3387-
MVT IVecVT = MVT::getVectorVT(MVT::getIntegerVT(EltVT.getSizeInBits()),
3387+
MVT IVecVT = MVT::getVectorVT(MVT::getIntegerVT(EltSize),
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VT.getVectorElementCount());
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unsigned ExtOpcode = Op.getOpcode() == ISD::UINT_TO_FP
33903390
? ISD::ZERO_EXTEND
@@ -3402,7 +3402,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
34023402
}
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34043404
// Narrowing conversions
3405-
if (SrcEltSize > EltSize && (SrcEltSize / EltSize >= 4)) {
3405+
if (SrcEltSize > (2 * EltSize)) {
34063406
if (IsInt2FP) {
34073407
// One narrowing int_to_fp, then an fp_round.
34083408
assert(EltVT == MVT::f16 && "Unexpected [US]_TO_FP lowering");
@@ -3413,9 +3413,8 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
34133413
// FP2Int
34143414
// One narrowing fp_to_int, then truncate the integer. If the float isn't
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// representable by the integer, the result is poison.
3416-
MVT IVecVT =
3417-
MVT::getVectorVT(MVT::getIntegerVT(SrcEltVT.getSizeInBits() / 2),
3418-
VT.getVectorElementCount());
3416+
MVT IVecVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize / 2),
3417+
VT.getVectorElementCount());
34193418
SDValue FP2Int = DAG.getNode(Op.getOpcode(), DL, IVecVT, Src);
34203419
return DAG.getNode(ISD::TRUNCATE, DL, VT, FP2Int);
34213420
}

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