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kosarevkosarev
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Revert "[AMDGPU] Introduce real and keep fake True16 instructions."
This reverts commit 0f864c7 due to failures on expensive checks.
1 parent 45e425e commit 6cb3866

14 files changed

+66
-144
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPU.td

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1693,15 +1693,6 @@ def HasTrue16BitInsts : Predicate<"Subtarget->hasTrue16BitInsts()">,
16931693
AssemblerPredicate<(all_of FeatureTrue16BitInsts)>;
16941694
def NotHasTrue16BitInsts : Predicate<"!Subtarget->hasTrue16BitInsts()">;
16951695

1696-
// Control use of True16 instructions. The real True16 instructions are
1697-
// True16 instructions as they are defined in the ISA. Fake True16
1698-
// instructions have the same encoding as real ones but syntactically
1699-
// only allow 32-bit registers in operands and use low halves thereof.
1700-
def UseRealTrue16Insts : Predicate<"Subtarget->useRealTrue16Insts()">,
1701-
AssemblerPredicate<(all_of FeatureTrue16BitInsts, FeatureRealTrue16Insts)>;
1702-
def UseFakeTrue16Insts : Predicate<"Subtarget->hasTrue16BitInsts() && "
1703-
"!Subtarget->useRealTrue16Insts()">;
1704-
17051696
def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
17061697
AssemblerPredicate<(all_of FeatureVOP3P)>;
17071698

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Lines changed: 6 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -420,14 +420,11 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
420420
// encodings
421421
if (isGFX11Plus() && Bytes.size() >= 12 ) {
422422
DecoderUInt128 DecW = eat12Bytes(Bytes);
423-
Res =
424-
tryDecodeInst(DecoderTableDPP8GFX1196, DecoderTableDPP8GFX11_FAKE1696,
425-
MI, DecW, Address, CS);
423+
Res = tryDecodeInst(DecoderTableDPP8GFX1196, MI, DecW, Address, CS);
426424
if (Res && convertDPP8Inst(MI) == MCDisassembler::Success)
427425
break;
428426
MI = MCInst(); // clear
429-
Res = tryDecodeInst(DecoderTableDPPGFX1196, DecoderTableDPPGFX11_FAKE1696,
430-
MI, DecW, Address, CS);
427+
Res = tryDecodeInst(DecoderTableDPPGFX1196, MI, DecW, Address, CS);
431428
if (Res) {
432429
if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P)
433430
convertVOP3PDPPInst(MI);
@@ -466,17 +463,15 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
466463
break;
467464
MI = MCInst(); // clear
468465

469-
Res = tryDecodeInst(DecoderTableDPP8GFX1164,
470-
DecoderTableDPP8GFX11_FAKE1664, MI, QW, Address, CS);
466+
Res = tryDecodeInst(DecoderTableDPP8GFX1164, MI, QW, Address, CS);
471467
if (Res && convertDPP8Inst(MI) == MCDisassembler::Success)
472468
break;
473469
MI = MCInst(); // clear
474470

475471
Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address, CS);
476472
if (Res) break;
477473

478-
Res = tryDecodeInst(DecoderTableDPPGFX1164, DecoderTableDPPGFX11_FAKE1664,
479-
MI, QW, Address, CS);
474+
Res = tryDecodeInst(DecoderTableDPPGFX1164, MI, QW, Address, CS);
480475
if (Res) {
481476
if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC)
482477
convertVOPCDPPInst(MI);
@@ -537,8 +532,7 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
537532
Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address, CS);
538533
if (Res) break;
539534

540-
Res = tryDecodeInst(DecoderTableGFX1132, DecoderTableGFX11_FAKE1632, MI, DW,
541-
Address, CS);
535+
Res = tryDecodeInst(DecoderTableGFX1132, MI, DW, Address, CS);
542536
if (Res) break;
543537

544538
if (Bytes.size() < 4) break;
@@ -568,8 +562,7 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
568562
Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address, CS);
569563
if (Res) break;
570564

571-
Res = tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664, MI, QW,
572-
Address, CS);
565+
Res = tryDecodeInst(DecoderTableGFX1164, MI, QW, Address, CS);
573566
if (Res)
574567
break;
575568

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h

Lines changed: 0 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -144,17 +144,6 @@ class AMDGPUDisassembler : public MCDisassembler {
144144
return MCDisassembler::Fail;
145145
}
146146

147-
template <typename InsnType>
148-
DecodeStatus tryDecodeInst(const uint8_t *Table1, const uint8_t *Table2,
149-
MCInst &MI, InsnType Inst, uint64_t Address,
150-
raw_ostream &Comments) const {
151-
for (const uint8_t *T : {Table1, Table2}) {
152-
if (DecodeStatus Res = tryDecodeInst(T, MI, Inst, Address, Comments))
153-
return Res;
154-
}
155-
return MCDisassembler::Fail;
156-
}
157-
158147
std::optional<DecodeStatus>
159148
onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef<uint8_t> Bytes,
160149
uint64_t Address, raw_ostream &CStream) const override;

‎llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

Lines changed: 4 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1408,7 +1408,6 @@ const MachineOperand *SIFoldOperands::isClamp(const MachineInstr &MI) const {
14081408
case AMDGPU::V_MAX_F32_e64:
14091409
case AMDGPU::V_MAX_F16_e64:
14101410
case AMDGPU::V_MAX_F16_t16_e64:
1411-
case AMDGPU::V_MAX_F16_fake16_e64:
14121411
case AMDGPU::V_MAX_F64_e64:
14131412
case AMDGPU::V_PK_MAX_F16: {
14141413
if (!TII->getNamedOperand(MI, AMDGPU::OpName::clamp)->getImm())
@@ -1504,8 +1503,7 @@ static int getOModValue(unsigned Opc, int64_t Val) {
15041503
}
15051504
}
15061505
case AMDGPU::V_MUL_F16_e64:
1507-
case AMDGPU::V_MUL_F16_t16_e64:
1508-
case AMDGPU::V_MUL_F16_fake16_e64: {
1506+
case AMDGPU::V_MUL_F16_t16_e64: {
15091507
switch (static_cast<uint16_t>(Val)) {
15101508
case 0x3800: // 0.5
15111509
return SIOutMods::DIV2;
@@ -1532,14 +1530,12 @@ SIFoldOperands::isOMod(const MachineInstr &MI) const {
15321530
case AMDGPU::V_MUL_F64_e64:
15331531
case AMDGPU::V_MUL_F32_e64:
15341532
case AMDGPU::V_MUL_F16_t16_e64:
1535-
case AMDGPU::V_MUL_F16_fake16_e64:
15361533
case AMDGPU::V_MUL_F16_e64: {
15371534
// If output denormals are enabled, omod is ignored.
15381535
if ((Op == AMDGPU::V_MUL_F32_e64 &&
15391536
MFI->getMode().FP32Denormals.Output != DenormalMode::PreserveSign) ||
15401537
((Op == AMDGPU::V_MUL_F64_e64 || Op == AMDGPU::V_MUL_F16_e64 ||
1541-
Op == AMDGPU::V_MUL_F16_t16_e64 ||
1542-
Op == AMDGPU::V_MUL_F16_fake16_e64) &&
1538+
Op == AMDGPU::V_MUL_F16_t16_e64) &&
15431539
MFI->getMode().FP64FP16Denormals.Output != DenormalMode::PreserveSign))
15441540
return std::pair(nullptr, SIOutMods::NONE);
15451541

@@ -1569,14 +1565,12 @@ SIFoldOperands::isOMod(const MachineInstr &MI) const {
15691565
case AMDGPU::V_ADD_F64_e64:
15701566
case AMDGPU::V_ADD_F32_e64:
15711567
case AMDGPU::V_ADD_F16_e64:
1572-
case AMDGPU::V_ADD_F16_t16_e64:
1573-
case AMDGPU::V_ADD_F16_fake16_e64: {
1568+
case AMDGPU::V_ADD_F16_t16_e64: {
15741569
// If output denormals are enabled, omod is ignored.
15751570
if ((Op == AMDGPU::V_ADD_F32_e64 &&
15761571
MFI->getMode().FP32Denormals.Output != DenormalMode::PreserveSign) ||
15771572
((Op == AMDGPU::V_ADD_F64_e64 || Op == AMDGPU::V_ADD_F16_e64 ||
1578-
Op == AMDGPU::V_ADD_F16_t16_e64 ||
1579-
Op == AMDGPU::V_ADD_F16_fake16_e64) &&
1573+
Op == AMDGPU::V_ADD_F16_t16_e64) &&
15801574
MFI->getMode().FP64FP16Denormals.Output != DenormalMode::PreserveSign))
15811575
return std::pair(nullptr, SIOutMods::NONE);
15821576

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 0 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -2262,7 +2262,6 @@ class VOPProfile <list<ValueType> _ArgVT, bit _EnableClamp = 0> {
22622262
field list<ValueType> ArgVT = _ArgVT;
22632263
field bit EnableClamp = _EnableClamp;
22642264
field bit IsTrue16 = 0;
2265-
field bit IsRealTrue16 = 0;
22662265

22672266
field ValueType DstVT = ArgVT[0];
22682267
field ValueType Src0VT = ArgVT[1];
@@ -2454,21 +2453,6 @@ class VOP_PAT_GEN <VOPProfile p, int mode=PatGenMode.NoPattern> : VOPProfile <p.
24542453
// VOPC_Class_NoSdst_Profile_t16, and VOP_MAC_F16_t16 do not inherit from this
24552454
// class, so copy changes to this class in those profiles
24562455
class VOPProfile_True16<VOPProfile P> : VOPProfile<P.ArgVT> {
2457-
let IsTrue16 = 1;
2458-
let IsRealTrue16 = 1;
2459-
// Most DstVT are 16-bit, but not all.
2460-
let DstRC = getVALUDstForVT_t16<DstVT>.ret;
2461-
let DstRC64 = getVALUDstForVT<DstVT>.ret;
2462-
let Src1RC32 = RegisterOperand<getVregSrcForVT_t16<Src1VT>.ret>;
2463-
let Src0DPP = getVregSrcForVT_t16<Src0VT>.ret;
2464-
let Src1DPP = getVregSrcForVT_t16<Src1VT>.ret;
2465-
let Src2DPP = getVregSrcForVT_t16<Src2VT>.ret;
2466-
let Src0ModDPP = getSrcModDPP_t16<Src0VT>.ret;
2467-
let Src1ModDPP = getSrcModDPP_t16<Src1VT>.ret;
2468-
let Src2ModDPP = getSrcModDPP_t16<Src2VT>.ret;
2469-
}
2470-
2471-
class VOPProfile_Fake16<VOPProfile P> : VOPProfile<P.ArgVT> {
24722456
let IsTrue16 = 1;
24732457
// Most DstVT are 16-bit, but not all
24742458
let DstRC = getVALUDstForVT_t16<DstVT>.ret;

‎llvm/lib/Target/AMDGPU/SIInstructions.td

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1641,10 +1641,8 @@ def : ClampPat<V_MAX_F32_e64, f32>;
16411641
def : ClampPat<V_MAX_F64_e64, f64>;
16421642
let SubtargetPredicate = NotHasTrue16BitInsts in
16431643
def : ClampPat<V_MAX_F16_e64, f16>;
1644-
let SubtargetPredicate = UseRealTrue16Insts in
1644+
let SubtargetPredicate = HasTrue16BitInsts in
16451645
def : ClampPat<V_MAX_F16_t16_e64, f16>;
1646-
let SubtargetPredicate = UseFakeTrue16Insts in
1647-
def : ClampPat<V_MAX_F16_fake16_e64, f16>;
16481646

16491647
let SubtargetPredicate = HasVOP3PInsts in {
16501648
def : GCNPat <
@@ -2698,12 +2696,12 @@ def : GCNPat<
26982696
let OtherPredicates = [HasTrue16BitInsts] in {
26992697
def : GCNPat<
27002698
(fcanonicalize (f16 (VOP3Mods f16:$src, i32:$src_mods))),
2701-
(V_MUL_F16_fake16_e64 0, (i32 CONST.FP16_ONE), $src_mods, $src)
2699+
(V_MUL_F16_t16_e64 0, (i32 CONST.FP16_ONE), $src_mods, $src)
27022700
>;
27032701

27042702
def : GCNPat<
27052703
(fcanonicalize (f16 (fneg (VOP3Mods f16:$src, i32:$src_mods)))),
2706-
(V_MUL_F16_fake16_e64 0, (i32 CONST.FP16_NEG_ONE), $src_mods, $src)
2704+
(V_MUL_F16_t16_e64 0, (i32 CONST.FP16_NEG_ONE), $src_mods, $src)
27072705
>;
27082706
} // End OtherPredicates
27092707

‎llvm/lib/Target/AMDGPU/VOP1Instructions.td

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -152,7 +152,7 @@ multiclass VOP1Inst_t16<string opName,
152152
defm NAME : VOP1Inst<opName, P, node>;
153153
}
154154
let OtherPredicates = [HasTrue16BitInsts] in {
155-
defm _t16 : VOP1Inst<opName#"_t16", VOPProfile_Fake16<P>, node>;
155+
defm _t16 : VOP1Inst<opName#"_t16", VOPProfile_True16<P>, node>;
156156
}
157157
}
158158

@@ -170,7 +170,7 @@ class VOPProfileI2F<ValueType dstVt, ValueType srcVt> :
170170
}
171171

172172
class VOPProfileI2F_True16<ValueType dstVt, ValueType srcVt> :
173-
VOPProfile_Fake16<VOPProfile<[dstVt, srcVt, untyped, untyped]>> {
173+
VOPProfile_True16<VOPProfile<[dstVt, srcVt, untyped, untyped]>> {
174174

175175
let Ins64 = (ins Src0RC64:$src0, clampmod:$clamp, omod:$omod);
176176
let InsVOP3Base = (ins Src0VOP3DPP:$src0, clampmod:$clamp, omod:$omod);
@@ -199,7 +199,7 @@ class VOP_SPECIAL_OMOD_PROF<ValueType dstVt, ValueType srcVt> :
199199
def VOP_I32_F32_SPECIAL_OMOD : VOP_SPECIAL_OMOD_PROF<i32, f32>;
200200
def VOP_I32_F64_SPECIAL_OMOD : VOP_SPECIAL_OMOD_PROF<i32, f64>;
201201
def VOP_I16_F16_SPECIAL_OMOD : VOP_SPECIAL_OMOD_PROF<i16, f16>;
202-
def VOP_I16_F16_SPECIAL_OMOD_t16 : VOPProfile_Fake16<VOP_I16_F16> {
202+
def VOP_I16_F16_SPECIAL_OMOD_t16 : VOPProfile_True16<VOP_I16_F16> {
203203
let HasOMod = 1;
204204
}
205205

@@ -292,13 +292,13 @@ let FPDPRounding = 1, isReMaterializable = 0 in {
292292
let OtherPredicates = [NotHasTrue16BitInsts] in
293293
defm V_CVT_F16_F32 : VOP1Inst <"v_cvt_f16_f32", VOP_F16_F32, any_fpround>;
294294
let OtherPredicates = [HasTrue16BitInsts] in
295-
defm V_CVT_F16_F32_t16 : VOP1Inst <"v_cvt_f16_f32_t16", VOPProfile_Fake16<VOP_F16_F32>, any_fpround>;
295+
defm V_CVT_F16_F32_t16 : VOP1Inst <"v_cvt_f16_f32_t16", VOPProfile_True16<VOP_F16_F32>, any_fpround>;
296296
} // End FPDPRounding = 1, isReMaterializable = 0
297297

298298
let OtherPredicates = [NotHasTrue16BitInsts] in
299299
defm V_CVT_F32_F16 : VOP1Inst <"v_cvt_f32_f16", VOP_F32_F16, any_fpextend>;
300300
let OtherPredicates = [HasTrue16BitInsts] in
301-
defm V_CVT_F32_F16_t16 : VOP1Inst <"v_cvt_f32_f16_t16", VOPProfile_Fake16<VOP_F32_F16>, any_fpextend>;
301+
defm V_CVT_F32_F16_t16 : VOP1Inst <"v_cvt_f32_f16_t16", VOPProfile_True16<VOP_F32_F16>, any_fpextend>;
302302

303303
let ReadsModeReg = 0, mayRaiseFPException = 0 in {
304304
defm V_CVT_RPI_I32_F32 : VOP1Inst <"v_cvt_rpi_i32_f32", VOP_I32_F32, cvt_rpi_i32_f32>;

‎llvm/lib/Target/AMDGPU/VOP2Instructions.td

Lines changed: 8 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -194,12 +194,9 @@ multiclass VOP2Inst_t16<string opName,
194194
let SubtargetPredicate = NotHasTrue16BitInsts, OtherPredicates = [Has16BitInsts] in {
195195
defm NAME : VOP2Inst<opName, P, node, revOp, GFX9Renamed>;
196196
}
197-
let SubtargetPredicate = UseRealTrue16Insts in {
197+
let SubtargetPredicate = HasTrue16BitInsts in {
198198
defm _t16 : VOP2Inst<opName#"_t16", VOPProfile_True16<P>, node, revOp#"_t16", GFX9Renamed>;
199199
}
200-
let SubtargetPredicate = UseFakeTrue16Insts in {
201-
defm _fake16 : VOP2Inst<opName#"_fake16", VOPProfile_Fake16<P>, node, revOp#"_fake16", GFX9Renamed>;
202-
}
203200
}
204201

205202
// Creating a _t16_e32 pseudo when there is no corresponding real instruction on
@@ -215,7 +212,7 @@ multiclass VOP2Inst_e64_t16<string opName,
215212
defm NAME : VOP2Inst<opName, P, node, revOp, GFX9Renamed>;
216213
}
217214
let SubtargetPredicate = HasTrue16BitInsts in {
218-
defm _t16 : VOP2Inst_e64<opName#"_t16", VOPProfile_Fake16<P>, node, revOp#"_t16", GFX9Renamed>;
215+
defm _t16 : VOP2Inst_e64<opName#"_t16", VOPProfile_True16<P>, node, revOp#"_t16", GFX9Renamed>;
219216
}
220217
}
221218

@@ -877,7 +874,7 @@ def LDEXP_F16_VOPProfile : VOPProfile <[f16, f16, f16, untyped]> {
877874
let HasSrc1FloatMods = 0;
878875
let Src1ModSDWA = Int16SDWAInputMods;
879876
}
880-
def LDEXP_F16_VOPProfile_True16 : VOPProfile_Fake16<VOP_F16_F16_F16> {
877+
def LDEXP_F16_VOPProfile_True16 : VOPProfile_True16<VOP_F16_F16_F16> {
881878
let Src1RC32 = RegisterOperand<VGPR_32_Lo128>;
882879
let Src1DPP = VGPR_32_Lo128;
883880
let Src1ModDPP = IntT16VRegInputMods;
@@ -928,9 +925,9 @@ def : LDEXP_F16_Pat<any_fldexp, V_LDEXP_F16_t16_e64>;
928925

929926
let SubtargetPredicate = isGFX11Plus in {
930927
let isCommutable = 1 in {
931-
defm V_AND_B16_t16 : VOP2Inst_e64 <"v_and_b16_t16", VOPProfile_Fake16<VOP_I16_I16_I16>, and>;
932-
defm V_OR_B16_t16 : VOP2Inst_e64 <"v_or_b16_t16", VOPProfile_Fake16<VOP_I16_I16_I16>, or>;
933-
defm V_XOR_B16_t16 : VOP2Inst_e64 <"v_xor_b16_t16", VOPProfile_Fake16<VOP_I16_I16_I16>, xor>;
928+
defm V_AND_B16_t16 : VOP2Inst_e64 <"v_and_b16_t16", VOPProfile_True16<VOP_I16_I16_I16>, and>;
929+
defm V_OR_B16_t16 : VOP2Inst_e64 <"v_or_b16_t16", VOPProfile_True16<VOP_I16_I16_I16>, or>;
930+
defm V_XOR_B16_t16 : VOP2Inst_e64 <"v_xor_b16_t16", VOPProfile_True16<VOP_I16_I16_I16>, xor>;
934931
} // End isCommutable = 1
935932
} // End SubtargetPredicate = isGFX11Plus
936933

@@ -1310,8 +1307,6 @@ let AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11" in {
13101307
multiclass VOP2_Real_e32_with_name_gfx11<bits<6> op, string opName,
13111308
string asmName, bit single = 0> {
13121309
defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");
1313-
let DecoderNamespace = !if(ps.Pfl.IsRealTrue16, "GFX11", "GFX11_FAKE16"),
1314-
AssemblerPredicate = !if(ps.Pfl.IsRealTrue16, UseRealTrue16Insts, isGFX11Only) in
13151310
def _e32_gfx11 :
13161311
VOP2_Real<ps, SIEncodingFamily.GFX11, asmName>,
13171312
VOP2e<op{5-0}, ps.Pfl> {
@@ -1336,8 +1331,7 @@ let AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11" in {
13361331
def _dpp_gfx11 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"),
13371332
SIEncodingFamily.GFX11> {
13381333
let AsmString = asmName # ps.Pfl.AsmDPP16;
1339-
let DecoderNamespace = !if(ps.Pfl.IsRealTrue16, "DPPGFX11", "DPPGFX11_FAKE16");
1340-
let AssemblerPredicate = !if(ps.Pfl.IsRealTrue16, UseRealTrue16Insts, isGFX11Only);
1334+
let DecoderNamespace = "DPPGFX11";
13411335
}
13421336
}
13431337
multiclass VOP2_Real_dpp8_with_name_gfx11<bits<6> op, string opName,
@@ -1346,8 +1340,7 @@ let AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11" in {
13461340
if ps.Pfl.HasExtDPP then
13471341
def _dpp8_gfx11 : VOP2_DPP8<op, ps> {
13481342
let AsmString = asmName # ps.Pfl.AsmDPP8;
1349-
let DecoderNamespace = !if(ps.Pfl.IsRealTrue16, "DPP8GFX11", "DPP8GFX11_FAKE16");
1350-
let AssemblerPredicate = !if(ps.Pfl.IsRealTrue16, UseRealTrue16Insts, isGFX11Only);
1343+
let DecoderNamespace = "DPP8GFX11";
13511344
}
13521345
}
13531346

@@ -1498,19 +1491,13 @@ defm V_CVT_PK_RTZ_F16_F32 : VOP2_Real_FULL_with_name_gfx11<0x02f,
14981491
defm V_PK_FMAC_F16 : VOP2Only_Real_gfx11<0x03c>;
14991492

15001493
defm V_ADD_F16_t16 : VOP2_Real_FULL_t16_gfx11<0x032, "v_add_f16">;
1501-
defm V_ADD_F16_fake16 : VOP2_Real_FULL_t16_gfx11<0x032, "v_add_f16">;
15021494
defm V_SUB_F16_t16 : VOP2_Real_FULL_t16_gfx11<0x033, "v_sub_f16">;
1503-
defm V_SUB_F16_fake16 : VOP2_Real_FULL_t16_gfx11<0x033, "v_sub_f16">;
15041495
defm V_SUBREV_F16_t16 : VOP2_Real_FULL_t16_gfx11<0x034, "v_subrev_f16">;
1505-
defm V_SUBREV_F16_fake16 : VOP2_Real_FULL_t16_gfx11<0x034, "v_subrev_f16">;
15061496
defm V_MUL_F16_t16 : VOP2_Real_FULL_t16_gfx11<0x035, "v_mul_f16">;
1507-
defm V_MUL_F16_fake16 : VOP2_Real_FULL_t16_gfx11<0x035, "v_mul_f16">;
15081497
defm V_FMAC_F16_t16 : VOP2_Real_FULL_t16_gfx11<0x036, "v_fmac_f16">;
15091498
defm V_LDEXP_F16_t16 : VOP2_Real_FULL_t16_gfx11<0x03b, "v_ldexp_f16">;
15101499
defm V_MAX_F16_t16 : VOP2_Real_FULL_t16_gfx11<0x039, "v_max_f16">;
1511-
defm V_MAX_F16_fake16 : VOP2_Real_FULL_t16_gfx11<0x039, "v_max_f16">;
15121500
defm V_MIN_F16_t16 : VOP2_Real_FULL_t16_gfx11<0x03a, "v_min_f16">;
1513-
defm V_MIN_F16_fake16 : VOP2_Real_FULL_t16_gfx11<0x03a, "v_min_f16">;
15141501
defm V_FMAMK_F16_t16 : VOP2Only_Real_MADK_gfx11_with_name<0x037, "v_fmamk_f16">;
15151502
defm V_FMAAK_F16_t16 : VOP2Only_Real_MADK_gfx11_with_name<0x038, "v_fmaak_f16">;
15161503

‎llvm/lib/Target/AMDGPU/VOPInstructions.td

Lines changed: 2 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1358,8 +1358,6 @@ let AssemblerPredicate = isGFX11Only,
13581358
VOP3_Real<ps, SIEncodingFamily.GFX11>,
13591359
VOP3OpSel_gfx11<op, ps.Pfl>;
13601360
if !not(ps.Pfl.HasOpSel) then
1361-
let DecoderNamespace = !if(ps.Pfl.IsRealTrue16, "GFX11", "GFX11_FAKE16"),
1362-
AssemblerPredicate = !if(ps.Pfl.IsRealTrue16, UseRealTrue16Insts, isGFX11Only) in
13631361
def _e64_gfx11 :
13641362
VOP3_Real<ps, SIEncodingFamily.GFX11>,
13651363
VOP3e_gfx11<op, ps.Pfl>;
@@ -1390,9 +1388,7 @@ let AssemblerPredicate = isGFX11Only,
13901388
multiclass VOP3_Real_dpp_with_name_gfx11<bits<10> op, string opName,
13911389
string asmName> {
13921390
defvar ps = !cast<VOP3_Pseudo>(opName#"_e64");
1393-
let AsmString = asmName # ps.Pfl.AsmVOP3DPP16,
1394-
DecoderNamespace = !if(ps.Pfl.IsRealTrue16, "DPPGFX11", "DPPGFX11_FAKE16"),
1395-
AssemblerPredicate = !if(ps.Pfl.IsRealTrue16, UseRealTrue16Insts, isGFX11Only) in {
1391+
let AsmString = asmName # ps.Pfl.AsmVOP3DPP16, DecoderNamespace = "DPPGFX11" in {
13961392
defm NAME : VOP3_Real_dpp_Base_gfx11<op, opName>;
13971393
}
13981394
}
@@ -1415,9 +1411,7 @@ let AssemblerPredicate = isGFX11Only,
14151411
multiclass VOP3_Real_dpp8_with_name_gfx11<bits<10> op, string opName,
14161412
string asmName> {
14171413
defvar ps = !cast<VOP3_Pseudo>(opName#"_e64");
1418-
let AsmString = asmName # ps.Pfl.AsmVOP3DPP8,
1419-
DecoderNamespace = !if(ps.Pfl.IsRealTrue16, "DPP8GFX11", "DPP8GFX11_FAKE16"),
1420-
AssemblerPredicate = !if(ps.Pfl.IsRealTrue16, UseRealTrue16Insts, isGFX11Only) in {
1414+
let AsmString = asmName # ps.Pfl.AsmVOP3DPP8, DecoderNamespace = "DPP8GFX11" in {
14211415
defm NAME : VOP3_Real_dpp8_Base_gfx11<op, opName>;
14221416
}
14231417
}

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