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[RISCV] Add Precommit test for D156685
Add baseline test for [[ https://reviews.llvm.org/D156685 | D156685 ]]. In LLVM, such signed 8 bits reaminder operation will first signed extened the operands to 32 bits, and then narrow the operands to the smaller bits data type such as 16 bits during the CorrelatedValuePropagation Pass to optimize the final data storage size. Such a signed extension operation for srem in LLVM system is to prevent the Undefined Behavior. Taking an example, -128 % -1 will lead to the Undefined Behaviour under the i8 type in LLVM IR, but this won't happen for i32, so such pattern cannot be eliminated in the platform-independent InstCombine Pass. The LLVM IR of these sext/trunc operations will be translated one by one during the RVV backend code generation process, and redundant vsetvli instructions will be inserted. In fact, according to the RVV instruction manual, the vrem.vv instruction has already specified the final output value of this type of overflow operation. For example, the overflow operation of -128 % -1 will get 0 according to the RISC-V spec, so through this patch , I think we can optimize these redundant rvv code through the SDNode pattern match at the instruction selection phase. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D157592
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‎llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll

Lines changed: 195 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,23 @@ define <vscale x 1 x i8> @vrem_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
4545
ret <vscale x 1 x i8> %vc
4646
}
4747

48+
define <vscale x 1 x i8> @vrem_vv_nxv1i8_sext_twice(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
49+
; CHECK-LABEL: vrem_vv_nxv1i8_sext_twice:
50+
; CHECK: # %bb.0:
51+
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
52+
; CHECK-NEXT: vsext.vf2 v10, v8
53+
; CHECK-NEXT: vsext.vf2 v8, v9
54+
; CHECK-NEXT: vrem.vv v8, v10, v8
55+
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
56+
; CHECK-NEXT: vnsrl.wi v8, v8, 0
57+
; CHECK-NEXT: ret
58+
%sext_va = sext <vscale x 1 x i8> %va to <vscale x 1 x i16>
59+
%sext_vb = sext <vscale x 1 x i8> %vb to <vscale x 1 x i16>
60+
%vc_ext = srem <vscale x 1 x i16> %sext_va, %sext_vb
61+
%vc = trunc <vscale x 1 x i16> %vc_ext to <vscale x 1 x i8>
62+
ret <vscale x 1 x i8> %vc
63+
}
64+
4865
define <vscale x 2 x i8> @vrem_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
4966
; CHECK-LABEL: vrem_vv_nxv2i8:
5067
; CHECK: # %bb.0:
@@ -86,6 +103,23 @@ define <vscale x 2 x i8> @vrem_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
86103
ret <vscale x 2 x i8> %vc
87104
}
88105

106+
define <vscale x 2 x i8> @vrem_vv_nxv2i8_sext_twice(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
107+
; CHECK-LABEL: vrem_vv_nxv2i8_sext_twice:
108+
; CHECK: # %bb.0:
109+
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
110+
; CHECK-NEXT: vsext.vf2 v10, v8
111+
; CHECK-NEXT: vsext.vf2 v8, v9
112+
; CHECK-NEXT: vrem.vv v8, v10, v8
113+
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
114+
; CHECK-NEXT: vnsrl.wi v8, v8, 0
115+
; CHECK-NEXT: ret
116+
%sext_va = sext <vscale x 2 x i8> %va to <vscale x 2 x i16>
117+
%sext_vb = sext <vscale x 2 x i8> %vb to <vscale x 2 x i16>
118+
%vc_ext = srem <vscale x 2 x i16> %sext_va, %sext_vb
119+
%vc = trunc <vscale x 2 x i16> %vc_ext to <vscale x 2 x i8>
120+
ret <vscale x 2 x i8> %vc
121+
}
122+
89123
define <vscale x 4 x i8> @vrem_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
90124
; CHECK-LABEL: vrem_vv_nxv4i8:
91125
; CHECK: # %bb.0:
@@ -127,6 +161,23 @@ define <vscale x 4 x i8> @vrem_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
127161
ret <vscale x 4 x i8> %vc
128162
}
129163

164+
define <vscale x 4 x i8> @vrem_vv_nxv4i8_sext_twice(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
165+
; CHECK-LABEL: vrem_vv_nxv4i8_sext_twice:
166+
; CHECK: # %bb.0:
167+
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
168+
; CHECK-NEXT: vsext.vf2 v10, v8
169+
; CHECK-NEXT: vsext.vf2 v8, v9
170+
; CHECK-NEXT: vrem.vv v8, v10, v8
171+
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
172+
; CHECK-NEXT: vnsrl.wi v8, v8, 0
173+
; CHECK-NEXT: ret
174+
%sext_va = sext <vscale x 4 x i8> %va to <vscale x 4 x i16>
175+
%sext_vb = sext <vscale x 4 x i8> %vb to <vscale x 4 x i16>
176+
%vc_ext = srem <vscale x 4 x i16> %sext_va, %sext_vb
177+
%vc = trunc <vscale x 4 x i16> %vc_ext to <vscale x 4 x i8>
178+
ret <vscale x 4 x i8> %vc
179+
}
180+
130181
define <vscale x 8 x i8> @vrem_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
131182
; CHECK-LABEL: vrem_vv_nxv8i8:
132183
; CHECK: # %bb.0:
@@ -168,6 +219,23 @@ define <vscale x 8 x i8> @vrem_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
168219
ret <vscale x 8 x i8> %vc
169220
}
170221

222+
define <vscale x 8 x i8> @vrem_vv_nxv8i8_sext_twice(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
223+
; CHECK-LABEL: vrem_vv_nxv8i8_sext_twice:
224+
; CHECK: # %bb.0:
225+
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
226+
; CHECK-NEXT: vsext.vf2 v10, v8
227+
; CHECK-NEXT: vsext.vf2 v12, v9
228+
; CHECK-NEXT: vrem.vv v10, v10, v12
229+
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
230+
; CHECK-NEXT: vnsrl.wi v8, v10, 0
231+
; CHECK-NEXT: ret
232+
%sext_va = sext <vscale x 8 x i8> %va to <vscale x 8 x i16>
233+
%sext_vb = sext <vscale x 8 x i8> %vb to <vscale x 8 x i16>
234+
%vc_ext = srem <vscale x 8 x i16> %sext_va, %sext_vb
235+
%vc = trunc <vscale x 8 x i16> %vc_ext to <vscale x 8 x i8>
236+
ret <vscale x 8 x i8> %vc
237+
}
238+
171239
define <vscale x 16 x i8> @vrem_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
172240
; CHECK-LABEL: vrem_vv_nxv16i8:
173241
; CHECK: # %bb.0:
@@ -209,6 +277,23 @@ define <vscale x 16 x i8> @vrem_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
209277
ret <vscale x 16 x i8> %vc
210278
}
211279

280+
define <vscale x 16 x i8> @vrem_vv_nxv16i8_sext_twice(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
281+
; CHECK-LABEL: vrem_vv_nxv16i8_sext_twice:
282+
; CHECK: # %bb.0:
283+
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
284+
; CHECK-NEXT: vsext.vf2 v12, v8
285+
; CHECK-NEXT: vsext.vf2 v16, v10
286+
; CHECK-NEXT: vrem.vv v12, v12, v16
287+
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
288+
; CHECK-NEXT: vnsrl.wi v8, v12, 0
289+
; CHECK-NEXT: ret
290+
%sext_va = sext <vscale x 16 x i8> %va to <vscale x 16 x i16>
291+
%sext_vb = sext <vscale x 16 x i8> %vb to <vscale x 16 x i16>
292+
%vc_ext = srem <vscale x 16 x i16> %sext_va, %sext_vb
293+
%vc = trunc <vscale x 16 x i16> %vc_ext to <vscale x 16 x i8>
294+
ret <vscale x 16 x i8> %vc
295+
}
296+
212297
define <vscale x 32 x i8> @vrem_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
213298
; CHECK-LABEL: vrem_vv_nxv32i8:
214299
; CHECK: # %bb.0:
@@ -250,6 +335,23 @@ define <vscale x 32 x i8> @vrem_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
250335
ret <vscale x 32 x i8> %vc
251336
}
252337

338+
define <vscale x 32 x i8> @vrem_vv_nxv32i8_sext_twice(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
339+
; CHECK-LABEL: vrem_vv_nxv32i8_sext_twice:
340+
; CHECK: # %bb.0:
341+
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
342+
; CHECK-NEXT: vsext.vf2 v16, v8
343+
; CHECK-NEXT: vsext.vf2 v24, v12
344+
; CHECK-NEXT: vrem.vv v16, v16, v24
345+
; CHECK-NEXT: vsetvli zero, zero, e8, m4, ta, ma
346+
; CHECK-NEXT: vnsrl.wi v8, v16, 0
347+
; CHECK-NEXT: ret
348+
%sext_va = sext <vscale x 32 x i8> %va to <vscale x 32 x i16>
349+
%sext_vb = sext <vscale x 32 x i8> %vb to <vscale x 32 x i16>
350+
%vc_ext = srem <vscale x 32 x i16> %sext_va, %sext_vb
351+
%vc = trunc <vscale x 32 x i16> %vc_ext to <vscale x 32 x i8>
352+
ret <vscale x 32 x i8> %vc
353+
}
354+
253355
define <vscale x 64 x i8> @vrem_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
254356
; CHECK-LABEL: vrem_vv_nxv64i8:
255357
; CHECK: # %bb.0:
@@ -345,6 +447,23 @@ define <vscale x 1 x i16> @vrem_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
345447
ret <vscale x 1 x i16> %vc
346448
}
347449

450+
define <vscale x 1 x i16> @vrem_vv_nxv1i16_sext_twice(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
451+
; CHECK-LABEL: vrem_vv_nxv1i16_sext_twice:
452+
; CHECK: # %bb.0:
453+
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
454+
; CHECK-NEXT: vsext.vf2 v10, v8
455+
; CHECK-NEXT: vsext.vf2 v8, v9
456+
; CHECK-NEXT: vrem.vv v8, v10, v8
457+
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
458+
; CHECK-NEXT: vnsrl.wi v8, v8, 0
459+
; CHECK-NEXT: ret
460+
%sext_va = sext <vscale x 1 x i16> %va to <vscale x 1 x i32>
461+
%sext_vb = sext <vscale x 1 x i16> %vb to <vscale x 1 x i32>
462+
%vc_ext = srem <vscale x 1 x i32> %sext_va, %sext_vb
463+
%vc = trunc <vscale x 1 x i32> %vc_ext to <vscale x 1 x i16>
464+
ret <vscale x 1 x i16> %vc
465+
}
466+
348467
define <vscale x 2 x i16> @vrem_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
349468
; CHECK-LABEL: vrem_vv_nxv2i16:
350469
; CHECK: # %bb.0:
@@ -399,6 +518,23 @@ define <vscale x 2 x i16> @vrem_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
399518
ret <vscale x 2 x i16> %vc
400519
}
401520

521+
define <vscale x 2 x i16> @vrem_vv_nxv2i16_sext_twice(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
522+
; CHECK-LABEL: vrem_vv_nxv2i16_sext_twice:
523+
; CHECK: # %bb.0:
524+
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
525+
; CHECK-NEXT: vsext.vf2 v10, v8
526+
; CHECK-NEXT: vsext.vf2 v8, v9
527+
; CHECK-NEXT: vrem.vv v8, v10, v8
528+
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
529+
; CHECK-NEXT: vnsrl.wi v8, v8, 0
530+
; CHECK-NEXT: ret
531+
%sext_va = sext <vscale x 2 x i16> %va to <vscale x 2 x i32>
532+
%sext_vb = sext <vscale x 2 x i16> %vb to <vscale x 2 x i32>
533+
%vc_ext = srem <vscale x 2 x i32> %sext_va, %sext_vb
534+
%vc = trunc <vscale x 2 x i32> %vc_ext to <vscale x 2 x i16>
535+
ret <vscale x 2 x i16> %vc
536+
}
537+
402538
define <vscale x 4 x i16> @vrem_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
403539
; CHECK-LABEL: vrem_vv_nxv4i16:
404540
; CHECK: # %bb.0:
@@ -453,6 +589,23 @@ define <vscale x 4 x i16> @vrem_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
453589
ret <vscale x 4 x i16> %vc
454590
}
455591

592+
define <vscale x 4 x i16> @vrem_vv_nxv4i16_sext_twice(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
593+
; CHECK-LABEL: vrem_vv_nxv4i16_sext_twice:
594+
; CHECK: # %bb.0:
595+
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
596+
; CHECK-NEXT: vsext.vf2 v10, v8
597+
; CHECK-NEXT: vsext.vf2 v12, v9
598+
; CHECK-NEXT: vrem.vv v10, v10, v12
599+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
600+
; CHECK-NEXT: vnsrl.wi v8, v10, 0
601+
; CHECK-NEXT: ret
602+
%sext_va = sext <vscale x 4 x i16> %va to <vscale x 4 x i32>
603+
%sext_vb = sext <vscale x 4 x i16> %vb to <vscale x 4 x i32>
604+
%vc_ext = srem <vscale x 4 x i32> %sext_va, %sext_vb
605+
%vc = trunc <vscale x 4 x i32> %vc_ext to <vscale x 4 x i16>
606+
ret <vscale x 4 x i16> %vc
607+
}
608+
456609
define <vscale x 8 x i16> @vrem_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
457610
; CHECK-LABEL: vrem_vv_nxv8i16:
458611
; CHECK: # %bb.0:
@@ -507,6 +660,23 @@ define <vscale x 8 x i16> @vrem_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
507660
ret <vscale x 8 x i16> %vc
508661
}
509662

663+
define <vscale x 8 x i16> @vrem_vv_nxv8i16_sext_twice(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
664+
; CHECK-LABEL: vrem_vv_nxv8i16_sext_twice:
665+
; CHECK: # %bb.0:
666+
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
667+
; CHECK-NEXT: vsext.vf2 v12, v8
668+
; CHECK-NEXT: vsext.vf2 v16, v10
669+
; CHECK-NEXT: vrem.vv v12, v12, v16
670+
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
671+
; CHECK-NEXT: vnsrl.wi v8, v12, 0
672+
; CHECK-NEXT: ret
673+
%sext_va = sext <vscale x 8 x i16> %va to <vscale x 8 x i32>
674+
%sext_vb = sext <vscale x 8 x i16> %vb to <vscale x 8 x i32>
675+
%vc_ext = srem <vscale x 8 x i32> %sext_va, %sext_vb
676+
%vc = trunc <vscale x 8 x i32> %vc_ext to <vscale x 8 x i16>
677+
ret <vscale x 8 x i16> %vc
678+
}
679+
510680
define <vscale x 16 x i16> @vrem_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
511681
; CHECK-LABEL: vrem_vv_nxv16i16:
512682
; CHECK: # %bb.0:
@@ -561,6 +731,23 @@ define <vscale x 16 x i16> @vrem_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
561731
ret <vscale x 16 x i16> %vc
562732
}
563733

734+
define <vscale x 16 x i16> @vrem_vv_nxv16i16_sext_twice(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
735+
; CHECK-LABEL: vrem_vv_nxv16i16_sext_twice:
736+
; CHECK: # %bb.0:
737+
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
738+
; CHECK-NEXT: vsext.vf2 v16, v8
739+
; CHECK-NEXT: vsext.vf2 v24, v12
740+
; CHECK-NEXT: vrem.vv v16, v16, v24
741+
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
742+
; CHECK-NEXT: vnsrl.wi v8, v16, 0
743+
; CHECK-NEXT: ret
744+
%sext_va = sext <vscale x 16 x i16> %va to <vscale x 16 x i32>
745+
%sext_vb = sext <vscale x 16 x i16> %vb to <vscale x 16 x i32>
746+
%vc_ext = srem <vscale x 16 x i32> %sext_va, %sext_vb
747+
%vc = trunc <vscale x 16 x i32> %vc_ext to <vscale x 16 x i16>
748+
ret <vscale x 16 x i16> %vc
749+
}
750+
564751
define <vscale x 32 x i16> @vrem_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
565752
; CHECK-LABEL: vrem_vv_nxv32i16:
566753
; CHECK: # %bb.0:
@@ -963,8 +1150,8 @@ define <vscale x 1 x i64> @vrem_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
9631150
;
9641151
; RV64-V-LABEL: vrem_vi_nxv1i64_0:
9651152
; RV64-V: # %bb.0:
966-
; RV64-V-NEXT: lui a0, %hi(.LCPI56_0)
967-
; RV64-V-NEXT: ld a0, %lo(.LCPI56_0)(a0)
1153+
; RV64-V-NEXT: lui a0, %hi(.LCPI67_0)
1154+
; RV64-V-NEXT: ld a0, %lo(.LCPI67_0)(a0)
9681155
; RV64-V-NEXT: vsetvli a1, zero, e64, m1, ta, ma
9691156
; RV64-V-NEXT: vmulh.vx v9, v8, a0
9701157
; RV64-V-NEXT: li a0, 63
@@ -1048,8 +1235,8 @@ define <vscale x 2 x i64> @vrem_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
10481235
;
10491236
; RV64-V-LABEL: vrem_vi_nxv2i64_0:
10501237
; RV64-V: # %bb.0:
1051-
; RV64-V-NEXT: lui a0, %hi(.LCPI59_0)
1052-
; RV64-V-NEXT: ld a0, %lo(.LCPI59_0)(a0)
1238+
; RV64-V-NEXT: lui a0, %hi(.LCPI70_0)
1239+
; RV64-V-NEXT: ld a0, %lo(.LCPI70_0)(a0)
10531240
; RV64-V-NEXT: vsetvli a1, zero, e64, m2, ta, ma
10541241
; RV64-V-NEXT: vmulh.vx v10, v8, a0
10551242
; RV64-V-NEXT: li a0, 63
@@ -1133,8 +1320,8 @@ define <vscale x 4 x i64> @vrem_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
11331320
;
11341321
; RV64-V-LABEL: vrem_vi_nxv4i64_0:
11351322
; RV64-V: # %bb.0:
1136-
; RV64-V-NEXT: lui a0, %hi(.LCPI62_0)
1137-
; RV64-V-NEXT: ld a0, %lo(.LCPI62_0)(a0)
1323+
; RV64-V-NEXT: lui a0, %hi(.LCPI73_0)
1324+
; RV64-V-NEXT: ld a0, %lo(.LCPI73_0)(a0)
11381325
; RV64-V-NEXT: vsetvli a1, zero, e64, m4, ta, ma
11391326
; RV64-V-NEXT: vmulh.vx v12, v8, a0
11401327
; RV64-V-NEXT: li a0, 63
@@ -1218,8 +1405,8 @@ define <vscale x 8 x i64> @vrem_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
12181405
;
12191406
; RV64-V-LABEL: vrem_vi_nxv8i64_0:
12201407
; RV64-V: # %bb.0:
1221-
; RV64-V-NEXT: lui a0, %hi(.LCPI65_0)
1222-
; RV64-V-NEXT: ld a0, %lo(.LCPI65_0)(a0)
1408+
; RV64-V-NEXT: lui a0, %hi(.LCPI76_0)
1409+
; RV64-V-NEXT: ld a0, %lo(.LCPI76_0)(a0)
12231410
; RV64-V-NEXT: vsetvli a1, zero, e64, m8, ta, ma
12241411
; RV64-V-NEXT: vmulh.vx v16, v8, a0
12251412
; RV64-V-NEXT: li a0, 63

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