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Jessica Paquette
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[AArch64][GlobalISel] Mark some vector G_ABS cases as legal
Each of the cases marked as legal here have an imported pattern in AArch64GenGlobalISel.inc. So, if we mark them as legal, we get selection for free. Technically this is only supposed to happen if we have NEON support. But, we fall back if we don't have that in the legalizer right now. I suppose it'd be better to have a FIXME so we can write the testcase when the time comes. (Plus, it'd just fall back in selection if NEON isn't available, so it's not *wrong*, I guess?) This fixes some fallbacks in the test suite. (Also use `isScalar` from LegalityPredicates.cpp while we're here just to tidy things a little bit.) Differential Revision: https://reviews.llvm.org/D100916
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‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -686,8 +686,10 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
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getActionDefinitionsBuilder({G_BZERO, G_MEMCPY, G_MEMMOVE, G_MEMSET})
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.libcall();
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689-
getActionDefinitionsBuilder(G_ABS).lowerIf(
690-
[=](const LegalityQuery &Query) { return Query.Types[0].isScalar(); });
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// FIXME: Legal types are only legal with NEON.
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getActionDefinitionsBuilder(G_ABS)
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.lowerIf(isScalar(0))
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.legalFor(PackedVectorAllTypeList);
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692694
getActionDefinitionsBuilder(G_VECREDUCE_FADD)
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// We only have FADDP to do reduction-like operations. Lower the rest.

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-abs.mir

Lines changed: 114 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,3 +32,117 @@ body: |
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%1:_(s64) = G_ABS %0(s64)
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$x0 = COPY %1(s64)
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...
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---
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name: abs_v4s16
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: abs_v4s16
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
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; CHECK: [[ABS:%[0-9]+]]:_(<4 x s16>) = G_ABS [[COPY]]
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; CHECK: $d0 = COPY [[ABS]](<4 x s16>)
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; CHECK: RET_ReallyLR implicit $d0
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%0:_(<4 x s16>) = COPY $d0
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%1:_(<4 x s16>) = G_ABS %0
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$d0 = COPY %1(<4 x s16>)
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RET_ReallyLR implicit $d0
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...
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---
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name: abs_v8s16
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: abs_v8s16
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
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; CHECK: [[ABS:%[0-9]+]]:_(<8 x s16>) = G_ABS [[COPY]]
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; CHECK: $q0 = COPY [[ABS]](<8 x s16>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<8 x s16>) = COPY $q0
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%1:_(<8 x s16>) = G_ABS %0
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$q0 = COPY %1(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: abs_v2s32
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: abs_v2s32
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
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; CHECK: [[ABS:%[0-9]+]]:_(<2 x s32>) = G_ABS [[COPY]]
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; CHECK: $d0 = COPY [[ABS]](<2 x s32>)
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; CHECK: RET_ReallyLR implicit $d0
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%0:_(<2 x s32>) = COPY $d0
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%1:_(<2 x s32>) = G_ABS %0
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$d0 = COPY %1(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: abs_v4s32
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: abs_v4s32
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[ABS:%[0-9]+]]:_(<4 x s32>) = G_ABS [[COPY]]
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; CHECK: $q0 = COPY [[ABS]](<4 x s32>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<4 x s32>) = COPY $q0
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%1:_(<4 x s32>) = G_ABS %0
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$q0 = COPY %1(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: abs_v4s8
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: abs_v4s8
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
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; CHECK: [[ABS:%[0-9]+]]:_(<8 x s8>) = G_ABS [[COPY]]
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; CHECK: $d0 = COPY [[ABS]](<8 x s8>)
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; CHECK: RET_ReallyLR implicit $d0
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%0:_(<8 x s8>) = COPY $d0
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%1:_(<8 x s8>) = G_ABS %0
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$d0 = COPY %1(<8 x s8>)
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RET_ReallyLR implicit $d0
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...
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---
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name: abs_v16s8
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: abs_v16s8
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
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; CHECK: [[ABS:%[0-9]+]]:_(<16 x s8>) = G_ABS [[COPY]]
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; CHECK: $q0 = COPY [[ABS]](<16 x s8>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<16 x s8>) = COPY $q0
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%1:_(<16 x s8>) = G_ABS %0
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$q0 = COPY %1(<16 x s8>)
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RET_ReallyLR implicit $q0
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148+
...

‎llvm/test/CodeGen/AArch64/GlobalISel/select-abs.mir

Lines changed: 130 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,130 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-apple-ios -run-pass=instruction-select %s -o - | FileCheck %s
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...
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---
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name: v4s16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: v4s16
15+
; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[ABSv4i16_:%[0-9]+]]:fpr64 = ABSv4i16 [[COPY]]
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; CHECK: $d0 = COPY [[ABSv4i16_]]
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; CHECK: RET_ReallyLR implicit $d0
20+
%0:fpr(<4 x s16>) = COPY $d0
21+
%1:fpr(<4 x s16>) = G_ABS %0
22+
$d0 = COPY %1(<4 x s16>)
23+
RET_ReallyLR implicit $d0
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25+
...
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---
27+
name: v8s16
28+
legalized: true
29+
regBankSelected: true
30+
tracksRegLiveness: true
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body: |
32+
bb.0:
33+
liveins: $q0
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; CHECK-LABEL: name: v8s16
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
38+
; CHECK: [[ABSv8i16_:%[0-9]+]]:fpr128 = ABSv8i16 [[COPY]]
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; CHECK: $q0 = COPY [[ABSv8i16_]]
40+
; CHECK: RET_ReallyLR implicit $q0
41+
%0:fpr(<8 x s16>) = COPY $q0
42+
%1:fpr(<8 x s16>) = G_ABS %0
43+
$q0 = COPY %1(<8 x s16>)
44+
RET_ReallyLR implicit $q0
45+
46+
...
47+
---
48+
name: v2s32
49+
legalized: true
50+
regBankSelected: true
51+
tracksRegLiveness: true
52+
body: |
53+
bb.0:
54+
liveins: $d0
55+
56+
; CHECK-LABEL: name: v2s32
57+
; CHECK: liveins: $d0
58+
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
59+
; CHECK: [[ABSv2i32_:%[0-9]+]]:fpr64 = ABSv2i32 [[COPY]]
60+
; CHECK: $d0 = COPY [[ABSv2i32_]]
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; CHECK: RET_ReallyLR implicit $d0
62+
%0:fpr(<2 x s32>) = COPY $d0
63+
%1:fpr(<2 x s32>) = G_ABS %0
64+
$d0 = COPY %1(<2 x s32>)
65+
RET_ReallyLR implicit $d0
66+
67+
...
68+
---
69+
name: v4s32
70+
legalized: true
71+
regBankSelected: true
72+
tracksRegLiveness: true
73+
body: |
74+
bb.0:
75+
liveins: $q0
76+
77+
; CHECK-LABEL: name: v4s32
78+
; CHECK: liveins: $q0
79+
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
80+
; CHECK: [[ABSv4i32_:%[0-9]+]]:fpr128 = ABSv4i32 [[COPY]]
81+
; CHECK: $q0 = COPY [[ABSv4i32_]]
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; CHECK: RET_ReallyLR implicit $q0
83+
%0:fpr(<4 x s32>) = COPY $q0
84+
%1:fpr(<4 x s32>) = G_ABS %0
85+
$q0 = COPY %1(<4 x s32>)
86+
RET_ReallyLR implicit $q0
87+
88+
...
89+
---
90+
name: v4s8
91+
legalized: true
92+
regBankSelected: true
93+
tracksRegLiveness: true
94+
body: |
95+
bb.0:
96+
liveins: $d0
97+
98+
; CHECK-LABEL: name: v4s8
99+
; CHECK: liveins: $d0
100+
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
101+
; CHECK: [[ABSv8i8_:%[0-9]+]]:fpr64 = ABSv8i8 [[COPY]]
102+
; CHECK: $d0 = COPY [[ABSv8i8_]]
103+
; CHECK: RET_ReallyLR implicit $d0
104+
%0:fpr(<8 x s8>) = COPY $d0
105+
%1:fpr(<8 x s8>) = G_ABS %0
106+
$d0 = COPY %1(<8 x s8>)
107+
RET_ReallyLR implicit $d0
108+
109+
...
110+
---
111+
name: v16s8
112+
legalized: true
113+
regBankSelected: true
114+
tracksRegLiveness: true
115+
body: |
116+
bb.0:
117+
liveins: $q0
118+
119+
; CHECK-LABEL: name: v16s8
120+
; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[ABSv16i8_:%[0-9]+]]:fpr128 = ABSv16i8 [[COPY]]
123+
; CHECK: $q0 = COPY [[ABSv16i8_]]
124+
; CHECK: RET_ReallyLR implicit $q0
125+
%0:fpr(<16 x s8>) = COPY $q0
126+
%1:fpr(<16 x s8>) = G_ABS %0
127+
$q0 = COPY %1(<16 x s8>)
128+
RET_ReallyLR implicit $q0
129+
130+
...

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