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[AArch64][GlobalISel] Combine G_UNMERGE(G_DUPLANE16) -> G_DUPLANE16 (#142731)
We will generate G_UNMERGE(G_DUPLANE16) due to the legalization of shuffle vector splats with mismatching vector sizes. The G_DUPLANE intrinsics can handle different vector sizes (128bit and 64bit output, for example), and we can combine away the unmerge.
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‎llvm/lib/Target/AArch64/AArch64Combine.td

Lines changed: 17 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -172,6 +172,21 @@ def form_duplane : GICombineRule <
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(apply [{ applyDupLane(*${root}, MRI, B, ${matchinfo}); }])
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>;
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// Clean up G_UNMERGE(G_DUPLANE16) -> G_DUPLANE16
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class unmerge_duplane<Instruction Op> : GICombineRule <
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(defs root:$root),
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(match (Op $a, $src, $c),
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(G_UNMERGE_VALUES $d1, $d2, $a):$root,
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[{ return MRI.getType(${d1}.getReg()).getSizeInBits() == 64; }]),
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(apply (GIReplaceReg $d2, $d1), (Op $d1, $src, $c))
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>;
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def unmerge_duplane8 : unmerge_duplane<G_DUPLANE8>;
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def unmerge_duplane16 : unmerge_duplane<G_DUPLANE16>;
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def unmerge_duplane32 : unmerge_duplane<G_DUPLANE32>;
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// G_DUPLANE64 is not included as the result in scalar.
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def unmerge_duplanes : GICombineGroup<[unmerge_duplane8, unmerge_duplane16,
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unmerge_duplane32]>;
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def shuffle_vector_lowering : GICombineGroup<[dup, form_duplane, rev, ext, zip,
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uzp, trn, fullrev, shuf_to_ins]>;
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@@ -325,7 +340,8 @@ def AArch64PostLegalizerLowering
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lower_vector_fcmp, form_truncstore,
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vector_sext_inreg_to_shift,
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unmerge_ext_to_unmerge, lower_mulv2s64,
328-
vector_unmerge_lowering, insertelt_nonconst]> {
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vector_unmerge_lowering, insertelt_nonconst,
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unmerge_duplanes]> {
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}
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331347
// Post-legalization combines which are primarily optimizations.

‎llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-unmergedup.mir

Lines changed: 91 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,91 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-lowering -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: unmerge_dup8
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legalized: true
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body: |
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bb.1.entry:
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; CHECK-LABEL: name: unmerge_dup8
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; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; CHECK-NEXT: [[DUPLANE8_:%[0-9]+]]:_(<8 x s8>) = G_DUPLANE8 [[COPY]], [[C]](s64)
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; CHECK-NEXT: $d0 = COPY [[DUPLANE8_]](<8 x s8>)
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; CHECK-NEXT: $d1 = COPY [[DUPLANE8_]](<8 x s8>)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%0:_(<16 x s8>) = COPY $q0
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%1:_(s64) = G_CONSTANT i64 1
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%2:_(<16 x s8>) = G_DUPLANE8 %0, %1
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%3:_(<8 x s8>), %4:_(<8 x s8>) = G_UNMERGE_VALUES %2
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$d0 = COPY %3
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$d1 = COPY %4
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RET_ReallyLR implicit $x0
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...
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---
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name: unmerge_dup16
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legalized: true
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body: |
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bb.1.entry:
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; CHECK-LABEL: name: unmerge_dup16
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; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; CHECK-NEXT: [[DUPLANE16_:%[0-9]+]]:_(<4 x s16>) = G_DUPLANE16 [[COPY]], [[C]](s64)
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; CHECK-NEXT: $d0 = COPY [[DUPLANE16_]](<4 x s16>)
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; CHECK-NEXT: $d1 = COPY [[DUPLANE16_]](<4 x s16>)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%0:_(<8 x s16>) = COPY $q0
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%1:_(s64) = G_CONSTANT i64 1
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%2:_(<8 x s16>) = G_DUPLANE16 %0, %1
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%3:_(<4 x s16>), %4:_(<4 x s16>) = G_UNMERGE_VALUES %2
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$d0 = COPY %3
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$d1 = COPY %4
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RET_ReallyLR implicit $x0
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...
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---
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name: unmerge_dup32
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legalized: true
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body: |
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bb.1.entry:
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; CHECK-LABEL: name: unmerge_dup32
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; CHECK-NEXT: [[DUPLANE32_:%[0-9]+]]:_(<2 x s32>) = G_DUPLANE32 [[COPY]], [[C]](s64)
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; CHECK-NEXT: $d0 = COPY [[DUPLANE32_]](<2 x s32>)
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; CHECK-NEXT: $d1 = COPY [[DUPLANE32_]](<2 x s32>)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%0:_(<4 x s32>) = COPY $q0
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%1:_(s64) = G_CONSTANT i64 1
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%2:_(<4 x s32>) = G_DUPLANE32 %0, %1
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%3:_(<2 x s32>), %4:_(<2 x s32>) = G_UNMERGE_VALUES %2
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$d0 = COPY %3
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$d1 = COPY %4
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RET_ReallyLR implicit $x0
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66+
...
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---
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name: unmerge_dup64
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legalized: true
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body: |
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bb.1.entry:
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; CHECK-LABEL: name: unmerge_dup64
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; CHECK-NEXT: [[DUPLANE64_:%[0-9]+]]:_(<2 x s64>) = G_DUPLANE64 [[COPY]], [[C]](s64)
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DUPLANE64_]](<2 x s64>), [[C1]](s64)
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DUPLANE64_]](<2 x s64>), [[C2]](s64)
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; CHECK-NEXT: $d0 = COPY [[EVEC]](s64)
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; CHECK-NEXT: $d1 = COPY [[EVEC1]](s64)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
83+
%0:_(<2 x s64>) = COPY $q0
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%1:_(s64) = G_CONSTANT i64 1
85+
%2:_(<2 x s64>) = G_DUPLANE64 %0, %1
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%3:_(s64), %4:_(s64) = G_UNMERGE_VALUES %2
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$d0 = COPY %3
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$d1 = COPY %4
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RET_ReallyLR implicit $x0
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91+
...

‎llvm/test/CodeGen/AArch64/arm64-dup.ll

Lines changed: 4 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -401,16 +401,10 @@ define <4 x i16> @test_build_illegal(<4 x i32> %in) {
401401
; SelectionDAGBuilder here. We then added a DUPLANE on top of that, preventing
402402
; the formation of an indexed-by-7 MLS.
403403
define <4 x i16> @test_high_splat(<4 x i16> %a, <4 x i16> %b, <8 x i16> %v) #0 {
404-
; CHECK-SD-LABEL: test_high_splat:
405-
; CHECK-SD: // %bb.0: // %entry
406-
; CHECK-SD-NEXT: mls.4h v0, v1, v2[7]
407-
; CHECK-SD-NEXT: ret
408-
;
409-
; CHECK-GI-LABEL: test_high_splat:
410-
; CHECK-GI: // %bb.0: // %entry
411-
; CHECK-GI-NEXT: dup.8h v2, v2[7]
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; CHECK-GI-NEXT: mls.4h v0, v2, v1
413-
; CHECK-GI-NEXT: ret
404+
; CHECK-LABEL: test_high_splat:
405+
; CHECK: // %bb.0: // %entry
406+
; CHECK-NEXT: mls.4h v0, v1, v2[7]
407+
; CHECK-NEXT: ret
414408
entry:
415409
%shuffle = shufflevector <8 x i16> %v, <8 x i16> undef, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
416410
%mul = mul <4 x i16> %shuffle, %b

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