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[RISCV] Make fixed-point instructions commutable
This PR includes: * vsadd.vv/vsaddu.vv * vaadd.vv/vaaddu.vv * vsmul.vv Pull Request: #90372
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+27
-21
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3 files changed

+27
-21
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3132,6 +3132,11 @@ bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
31323132
case CASE_RVV_OPCODE_WIDEN(VWMACC_VV):
31333133
case CASE_RVV_OPCODE_WIDEN(VWMACCU_VV):
31343134
case CASE_RVV_OPCODE_UNMASK(VADC_VVM):
3135+
case CASE_RVV_OPCODE(VSADD_VV):
3136+
case CASE_RVV_OPCODE(VSADDU_VV):
3137+
case CASE_RVV_OPCODE(VAADD_VV):
3138+
case CASE_RVV_OPCODE(VAADDU_VV):
3139+
case CASE_RVV_OPCODE(VSMUL_VV):
31353140
// Operands 2 and 3 are commutable.
31363141
return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
31373142
case CASE_VFMA_SPLATS(FMADD):

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 16 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -2146,8 +2146,9 @@ multiclass VPseudoBinaryRoundingMode<VReg RetClass,
21462146
string Constraint = "",
21472147
int sew = 0,
21482148
int UsesVXRM = 1,
2149-
int TargetConstraintType = 1> {
2150-
let VLMul = MInfo.value, SEW=sew in {
2149+
int TargetConstraintType = 1,
2150+
bit Commutable = 0> {
2151+
let VLMul = MInfo.value, SEW=sew, isCommutable = Commutable in {
21512152
defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
21522153
def suffix : VPseudoBinaryNoMaskRoundingMode<RetClass, Op1Class, Op2Class,
21532154
Constraint, UsesVXRM,
@@ -2232,8 +2233,9 @@ multiclass VPseudoBinaryV_VV<LMULInfo m, string Constraint = "", int sew = 0, bi
22322233
defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, Constraint, sew, Commutable=Commutable>;
22332234
}
22342235

2235-
multiclass VPseudoBinaryV_VV_RM<LMULInfo m, string Constraint = ""> {
2236-
defm _VV : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, m.vrclass, m, Constraint>;
2236+
multiclass VPseudoBinaryV_VV_RM<LMULInfo m, string Constraint = "", bit Commutable = 0> {
2237+
defm _VV : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, m.vrclass, m, Constraint,
2238+
Commutable=Commutable>;
22372239
}
22382240

22392241
// Similar to VPseudoBinaryV_VV, but uses MxListF.
@@ -2715,10 +2717,11 @@ multiclass VPseudoVGTR_VV_VX_VI<Operand ImmType = simm5, string Constraint = "">
27152717
}
27162718
}
27172719

2718-
multiclass VPseudoVSALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
2720+
multiclass VPseudoVSALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = "",
2721+
bit Commutable = 0> {
27192722
foreach m = MxList in {
27202723
defvar mx = m.MX;
2721-
defm "" : VPseudoBinaryV_VV<m, Constraint>,
2724+
defm "" : VPseudoBinaryV_VV<m, Constraint, Commutable=Commutable>,
27222725
SchedBinary<"WriteVSALUV", "ReadVSALUV", "ReadVSALUX", mx,
27232726
forceMergeOpRead=true>;
27242727
defm "" : VPseudoBinaryV_VX<m, Constraint>,
@@ -2788,7 +2791,7 @@ multiclass VPseudoVSALU_VV_VX {
27882791
multiclass VPseudoVSMUL_VV_VX_RM {
27892792
foreach m = MxList in {
27902793
defvar mx = m.MX;
2791-
defm "" : VPseudoBinaryV_VV_RM<m>,
2794+
defm "" : VPseudoBinaryV_VV_RM<m, Commutable=1>,
27922795
SchedBinary<"WriteVSMulV", "ReadVSMulV", "ReadVSMulV", mx,
27932796
forceMergeOpRead=true>;
27942797
defm "" : VPseudoBinaryV_VX_RM<m>,
@@ -2797,10 +2800,10 @@ multiclass VPseudoVSMUL_VV_VX_RM {
27972800
}
27982801
}
27992802

2800-
multiclass VPseudoVAALU_VV_VX_RM {
2803+
multiclass VPseudoVAALU_VV_VX_RM<bit Commutable = 0> {
28012804
foreach m = MxList in {
28022805
defvar mx = m.MX;
2803-
defm "" : VPseudoBinaryV_VV_RM<m>,
2806+
defm "" : VPseudoBinaryV_VV_RM<m, Commutable=Commutable>,
28042807
SchedBinary<"WriteVAALUV", "ReadVAALUV", "ReadVAALUV", mx,
28052808
forceMergeOpRead=true>;
28062809
defm "" : VPseudoBinaryV_VX_RM<m>,
@@ -6448,17 +6451,17 @@ defm PseudoVMV_V : VPseudoUnaryVMV_V_X_I;
64486451
// 12.1. Vector Single-Width Saturating Add and Subtract
64496452
//===----------------------------------------------------------------------===//
64506453
let Defs = [VXSAT], hasSideEffects = 1 in {
6451-
defm PseudoVSADDU : VPseudoVSALU_VV_VX_VI;
6452-
defm PseudoVSADD : VPseudoVSALU_VV_VX_VI;
6454+
defm PseudoVSADDU : VPseudoVSALU_VV_VX_VI<Commutable=1>;
6455+
defm PseudoVSADD : VPseudoVSALU_VV_VX_VI<Commutable=1>;
64536456
defm PseudoVSSUBU : VPseudoVSALU_VV_VX;
64546457
defm PseudoVSSUB : VPseudoVSALU_VV_VX;
64556458
}
64566459

64576460
//===----------------------------------------------------------------------===//
64586461
// 12.2. Vector Single-Width Averaging Add and Subtract
64596462
//===----------------------------------------------------------------------===//
6460-
defm PseudoVAADDU : VPseudoVAALU_VV_VX_RM;
6461-
defm PseudoVAADD : VPseudoVAALU_VV_VX_RM;
6463+
defm PseudoVAADDU : VPseudoVAALU_VV_VX_RM<Commutable=1>;
6464+
defm PseudoVAADD : VPseudoVAALU_VV_VX_RM<Commutable=1>;
64626465
defm PseudoVASUBU : VPseudoVAALU_VV_VX_RM;
64636466
defm PseudoVASUB : VPseudoVAALU_VV_VX_RM;
64646467

‎llvm/test/CodeGen/RISCV/rvv/commutable.ll

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -724,10 +724,9 @@ define <vscale x 1 x i64> @commutable_vaadd_vv(<vscale x 1 x i64> %0, <vscale x
724724
; CHECK: # %bb.0: # %entry
725725
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
726726
; CHECK-NEXT: csrwi vxrm, 0
727-
; CHECK-NEXT: vaadd.vv v10, v8, v9
728-
; CHECK-NEXT: vaadd.vv v8, v9, v8
727+
; CHECK-NEXT: vaadd.vv v8, v8, v9
729728
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
730-
; CHECK-NEXT: vadd.vv v8, v10, v8
729+
; CHECK-NEXT: vadd.vv v8, v8, v8
731730
; CHECK-NEXT: ret
732731
entry:
733732
%a = call <vscale x 1 x i64> @llvm.riscv.vaadd.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen 0, iXLen %2)
@@ -743,7 +742,7 @@ define <vscale x 1 x i64> @commutable_vaadd_vv_masked(<vscale x 1 x i64> %0, <vs
743742
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
744743
; CHECK-NEXT: csrwi vxrm, 0
745744
; CHECK-NEXT: vaadd.vv v10, v8, v9, v0.t
746-
; CHECK-NEXT: vaadd.vv v8, v9, v8, v0.t
745+
; CHECK-NEXT: vaadd.vv v8, v8, v9, v0.t
747746
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
748747
; CHECK-NEXT: vadd.vv v8, v10, v8
749748
; CHECK-NEXT: ret
@@ -760,10 +759,9 @@ define <vscale x 1 x i64> @commutable_vaaddu_vv(<vscale x 1 x i64> %0, <vscale x
760759
; CHECK: # %bb.0: # %entry
761760
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
762761
; CHECK-NEXT: csrwi vxrm, 0
763-
; CHECK-NEXT: vaaddu.vv v10, v8, v9
764-
; CHECK-NEXT: vaaddu.vv v8, v9, v8
762+
; CHECK-NEXT: vaaddu.vv v8, v8, v9
765763
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
766-
; CHECK-NEXT: vadd.vv v8, v10, v8
764+
; CHECK-NEXT: vadd.vv v8, v8, v8
767765
; CHECK-NEXT: ret
768766
entry:
769767
%a = call <vscale x 1 x i64> @llvm.riscv.vaaddu.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen 0, iXLen %2)
@@ -779,7 +777,7 @@ define <vscale x 1 x i64> @commutable_vaaddu_vv_masked(<vscale x 1 x i64> %0, <v
779777
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
780778
; CHECK-NEXT: csrwi vxrm, 0
781779
; CHECK-NEXT: vaaddu.vv v10, v8, v9, v0.t
782-
; CHECK-NEXT: vaaddu.vv v8, v9, v8, v0.t
780+
; CHECK-NEXT: vaaddu.vv v8, v8, v9, v0.t
783781
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
784782
; CHECK-NEXT: vadd.vv v8, v10, v8
785783
; CHECK-NEXT: ret

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