Skip to content

Commit 6cee18b

Browse files
artagnonartagnon
committed
[LV] Improve a test, regen with UTC
1 parent 80bdfcd commit 6cee18b

File tree

1 file changed

+97
-25
lines changed

1 file changed

+97
-25
lines changed

‎llvm/test/Transforms/LoopVectorize/X86/reduction-crash.ll

Lines changed: 97 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -1,35 +1,107 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
12
; RUN: opt -S -aa-pipeline= -passes=loop-vectorize -mcpu=prescott < %s | FileCheck %s
23

34
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32-S128"
45
target triple = "i386-apple-darwin"
56

6-
; PR15344
7-
define void @test1(ptr nocapture %arg, i32 %arg1, i1 %arg2) nounwind {
8-
; CHECK-LABEL: @test1(
9-
; CHECK: preheader
10-
; CHECK: insertelement <2 x double> zeroinitializer, double %tmp, i32 0
11-
; CHECK: vector.memcheck
7+
define void @pr15344(ptr noalias %ar, ptr noalias %ar2, i32 %exit.limit, i1 %cond) {
8+
; CHECK-LABEL: define void @pr15344(
9+
; CHECK-SAME: ptr noalias [[AR:%.*]], ptr noalias [[AR2:%.*]], i32 [[EXIT_LIMIT:%.*]], i1 [[COND:%.*]]) #[[ATTR0:[0-9]+]] {
10+
; CHECK-NEXT: [[ENTRY:.*:]]
11+
; CHECK-NEXT: br label %[[PH:.*]]
12+
; CHECK: [[PH]]:
13+
; CHECK-NEXT: [[LD:%.*]] = load double, ptr null, align 8
14+
; CHECK-NEXT: br i1 [[COND]], label %[[LOOP_PREHEADER:.*]], label %[[EXIT:.*]]
15+
; CHECK: [[LOOP_PREHEADER]]:
16+
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[EXIT_LIMIT]], 10
17+
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
18+
; CHECK: [[VECTOR_MEMCHECK]]:
19+
; CHECK-NEXT: [[TMP0:%.*]] = shl i32 [[EXIT_LIMIT]], 2
20+
; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[AR2]], i32 [[TMP0]]
21+
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[EXIT_LIMIT]], 3
22+
; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[AR]], i32 [[TMP1]]
23+
; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[AR2]], [[SCEVGEP1]]
24+
; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[AR]], [[SCEVGEP]]
25+
; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]
26+
; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
27+
; CHECK: [[VECTOR_PH]]:
28+
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[EXIT_LIMIT]], 4
29+
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[EXIT_LIMIT]], [[N_MOD_VF]]
30+
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> zeroinitializer, double [[LD]], i32 0
31+
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
32+
; CHECK: [[VECTOR_BODY]]:
33+
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
34+
; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <2 x double> [ [[TMP2]], %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ]
35+
; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <2 x double> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]
36+
; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[INDEX]], 0
37+
; CHECK-NEXT: [[TMP4]] = fadd fast <2 x double> [[VEC_PHI]], splat (double 1.000000e+00)
38+
; CHECK-NEXT: [[TMP5]] = fadd fast <2 x double> [[VEC_PHI2]], splat (double 1.000000e+00)
39+
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds float, ptr [[AR2]], i32 [[TMP3]]
40+
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds float, ptr [[TMP6]], i32 0
41+
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds float, ptr [[TMP6]], i32 2
42+
; CHECK-NEXT: store <2 x float> splat (float 2.000000e+00), ptr [[TMP7]], align 4, !alias.scope [[META0:![0-9]+]], !noalias [[META3:![0-9]+]]
43+
; CHECK-NEXT: store <2 x float> splat (float 2.000000e+00), ptr [[TMP8]], align 4, !alias.scope [[META0]], !noalias [[META3]]
44+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
45+
; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
46+
; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
47+
; CHECK: [[MIDDLE_BLOCK]]:
48+
; CHECK-NEXT: [[BIN_RDX:%.*]] = fadd fast <2 x double> [[TMP5]], [[TMP4]]
49+
; CHECK-NEXT: [[TMP10:%.*]] = call fast double @llvm.vector.reduce.fadd.v2f64(double 0.000000e+00, <2 x double> [[BIN_RDX]])
50+
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[EXIT_LIMIT]], [[N_VEC]]
51+
; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT_LOOPEXIT:.*]], label %[[SCALAR_PH]]
52+
; CHECK: [[SCALAR_PH]]:
53+
; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi double [ [[TMP10]], %[[MIDDLE_BLOCK]] ], [ [[LD]], %[[LOOP_PREHEADER]] ], [ [[LD]], %[[VECTOR_MEMCHECK]] ]
54+
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[LOOP_PREHEADER]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
55+
; CHECK-NEXT: br label %[[LOOP:.*]]
56+
; CHECK: [[LOOP]]:
57+
; CHECK-NEXT: [[RDX:%.*]] = phi double [ [[FADD:%.*]], %[[LOOP]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ]
58+
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]
59+
; CHECK-NEXT: [[GEP_AR:%.*]] = getelementptr inbounds [16 x double], ptr [[AR]], i32 0, i32 [[IV]]
60+
; CHECK-NEXT: [[LD2:%.*]] = load double, ptr [[GEP_AR]], align 4
61+
; CHECK-NEXT: [[IV_NEXT]] = add nsw i32 [[IV]], 1
62+
; CHECK-NEXT: [[FADD]] = fadd fast double [[RDX]], 1.000000e+00
63+
; CHECK-NEXT: [[GEP_AR2:%.*]] = getelementptr inbounds float, ptr [[AR2]], i32 [[IV]]
64+
; CHECK-NEXT: store float 2.000000e+00, ptr [[GEP_AR2]], align 4
65+
; CHECK-NEXT: [[EXIT_COND:%.*]] = icmp eq i32 [[IV_NEXT]], [[EXIT_LIMIT]]
66+
; CHECK-NEXT: br i1 [[EXIT_COND]], label %[[EXIT_LOOPEXIT]], label %[[LOOP]], !llvm.loop [[LOOP8:![0-9]+]]
67+
; CHECK: [[EXIT_LOOPEXIT]]:
68+
; CHECK-NEXT: [[FADD_LCSSA:%.*]] = phi double [ [[FADD]], %[[LOOP]] ], [ [[TMP10]], %[[MIDDLE_BLOCK]] ]
69+
; CHECK-NEXT: br label %[[EXIT]]
70+
; CHECK: [[EXIT]]:
71+
; CHECK-NEXT: [[RET:%.*]] = phi double [ [[LD]], %[[PH]] ], [ [[FADD_LCSSA]], %[[EXIT_LOOPEXIT]] ]
72+
; CHECK-NEXT: ret void
73+
;
74+
entry:
75+
br label %ph
1276

13-
bb:
14-
br label %bb2
77+
ph:
78+
%ld = load double, ptr null, align 8
79+
br i1 %cond, label %loop, label %exit
1580

16-
bb2: ; preds = %bb
17-
%tmp = load double, ptr null, align 8
18-
br i1 %arg2, label %bb3, label %bb12
81+
loop:
82+
%rdx = phi double [ %fadd, %loop ], [ %ld, %ph ]
83+
%iv = phi i32 [ %iv.next, %loop ], [ 0, %ph ]
84+
%gep.ar = getelementptr inbounds [16 x double], ptr %ar, i32 0, i32 %iv
85+
%ld2 = load double, ptr %gep.ar, align 4
86+
%iv.next = add nsw i32 %iv, 1
87+
%fadd = fadd fast double %rdx, 1.0
88+
%gep.ar2 = getelementptr inbounds float, ptr %ar2, i32 %iv
89+
store float 2.0, ptr %gep.ar2, align 4
90+
%exit.cond = icmp eq i32 %iv.next, %exit.limit
91+
br i1 %exit.cond, label %exit, label %loop
1992

20-
bb3: ; preds = %bb3, %bb2
21-
%tmp4 = phi double [ %tmp9, %bb3 ], [ %tmp, %bb2 ]
22-
%tmp5 = phi i32 [ %tmp8, %bb3 ], [ 0, %bb2 ]
23-
%tmp6 = getelementptr inbounds [16 x double], ptr undef, i32 0, i32 %tmp5
24-
%tmp7 = load double, ptr %tmp6, align 4
25-
%tmp8 = add nsw i32 %tmp5, 1
26-
%tmp9 = fadd fast double %tmp4, undef
27-
%tmp10 = getelementptr inbounds float, ptr %arg, i32 %tmp5
28-
store float undef, ptr %tmp10, align 4
29-
%tmp11 = icmp eq i32 %tmp8, %arg1
30-
br i1 %tmp11, label %bb12, label %bb3
31-
32-
bb12: ; preds = %bb3, %bb2
33-
%tmp13 = phi double [ %tmp, %bb2 ], [ %tmp9, %bb3 ]
93+
exit:
94+
%ret = phi double [ %ld, %ph ], [ %fadd, %loop ]
3495
ret void
3596
}
97+
;.
98+
; CHECK: [[META0]] = !{[[META1:![0-9]+]]}
99+
; CHECK: [[META1]] = distinct !{[[META1]], [[META2:![0-9]+]]}
100+
; CHECK: [[META2]] = distinct !{[[META2]], !"LVerDomain"}
101+
; CHECK: [[META3]] = !{[[META4:![0-9]+]]}
102+
; CHECK: [[META4]] = distinct !{[[META4]], [[META2]]}
103+
; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META6:![0-9]+]], [[META7:![0-9]+]]}
104+
; CHECK: [[META6]] = !{!"llvm.loop.isvectorized", i32 1}
105+
; CHECK: [[META7]] = !{!"llvm.loop.unroll.runtime.disable"}
106+
; CHECK: [[LOOP8]] = distinct !{[[LOOP8]], [[META6]]}
107+
;.

0 commit comments

Comments
 (0)