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[X86] Support promoted ENQCMD, KEYLOCKER and USERMSR (#77293)
R16-R31 was added into GPRs in #70958, This patch supports the promoted ENQCMD, KEYLOCKER and USER-MSR instructions in EVEX space. RFC: https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4
1 parent df5e431 commit 6d0080b

20 files changed

+883
-94
lines changed

‎llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -140,7 +140,9 @@ enum attributeBits {
140140
ENUM_ENTRY(IC_EVEX, 1, "requires an EVEX prefix") \
141141
ENUM_ENTRY(IC_EVEX_NF, 2, "requires EVEX and NF prefix") \
142142
ENUM_ENTRY(IC_EVEX_XS, 2, "requires EVEX and the XS prefix") \
143+
ENUM_ENTRY(IC_EVEX_XS_ADSIZE, 3, "requires EVEX, XS and the ADSIZE prefix") \
143144
ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \
145+
ENUM_ENTRY(IC_EVEX_XD_ADSIZE, 3, "requires EVEX, XD and the ADSIZE prefix") \
144146
ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \
145147
ENUM_ENTRY(IC_EVEX_OPSIZE_NF, 3, "requires EVEX, NF and the OpSize prefix") \
146148
ENUM_ENTRY(IC_EVEX_OPSIZE_ADSIZE, 3, \

‎llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -941,6 +941,9 @@ static bool readOpcode(struct InternalInstruction *insn) {
941941
case VEX_LOB_MAP6:
942942
insn->opcodeType = MAP6;
943943
return consume(insn, insn->opcode);
944+
case VEX_LOB_MAP7:
945+
insn->opcodeType = MAP7;
946+
return consume(insn, insn->opcode);
944947
}
945948
} else if (insn->vectorExtensionType == TYPE_VEX_3B) {
946949
switch (mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])) {

‎llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

Lines changed: 12 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -5035,14 +5035,18 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
50355035
unsigned Opcode;
50365036
switch (IntNo) {
50375037
default: llvm_unreachable("Impossible intrinsic");
5038-
case Intrinsic::x86_encodekey128: Opcode = X86::ENCODEKEY128; break;
5039-
case Intrinsic::x86_encodekey256: Opcode = X86::ENCODEKEY256; break;
5038+
case Intrinsic::x86_encodekey128:
5039+
Opcode = GET_EGPR_IF_ENABLED(X86::ENCODEKEY128);
5040+
break;
5041+
case Intrinsic::x86_encodekey256:
5042+
Opcode = GET_EGPR_IF_ENABLED(X86::ENCODEKEY256);
5043+
break;
50405044
}
50415045

50425046
SDValue Chain = Node->getOperand(0);
50435047
Chain = CurDAG->getCopyToReg(Chain, dl, X86::XMM0, Node->getOperand(3),
50445048
SDValue());
5045-
if (Opcode == X86::ENCODEKEY256)
5049+
if (Opcode == X86::ENCODEKEY256 || Opcode == X86::ENCODEKEY256_EVEX)
50465050
Chain = CurDAG->getCopyToReg(Chain, dl, X86::XMM1, Node->getOperand(4),
50475051
Chain.getValue(1));
50485052

@@ -5514,7 +5518,6 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
55145518
LoReg = UseMULX ? X86::RDX : X86::RAX;
55155519
HiReg = X86::RDX;
55165520
break;
5517-
#undef GET_EGPR_IF_ENABLED
55185521
}
55195522

55205523
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
@@ -6394,17 +6397,18 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
63946397
default:
63956398
llvm_unreachable("Unexpected opcode!");
63966399
case X86ISD::AESENCWIDE128KL:
6397-
Opcode = X86::AESENCWIDE128KL;
6400+
Opcode = GET_EGPR_IF_ENABLED(X86::AESENCWIDE128KL);
63986401
break;
63996402
case X86ISD::AESDECWIDE128KL:
6400-
Opcode = X86::AESDECWIDE128KL;
6403+
Opcode = GET_EGPR_IF_ENABLED(X86::AESDECWIDE128KL);
64016404
break;
64026405
case X86ISD::AESENCWIDE256KL:
6403-
Opcode = X86::AESENCWIDE256KL;
6406+
Opcode = GET_EGPR_IF_ENABLED(X86::AESENCWIDE256KL);
64046407
break;
64056408
case X86ISD::AESDECWIDE256KL:
6406-
Opcode = X86::AESDECWIDE256KL;
6409+
Opcode = GET_EGPR_IF_ENABLED(X86::AESDECWIDE256KL);
64076410
break;
6411+
#undef GET_EGPR_IF_ENABLED
64086412
}
64096413

64106414
SDValue Chain = Node->getOperand(0);

‎llvm/lib/Target/X86/X86InstrKL.td

Lines changed: 57 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -14,61 +14,75 @@
1414

1515
//===----------------------------------------------------------------------===//
1616
// Key Locker instructions
17+
class Encodekey<bits<8> opcode, string m>
18+
: I<opcode, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), m#"\t{$src, $dst|$dst, $src}", []>,
19+
NoCD8, XS;
1720

18-
let SchedRW = [WriteSystem], Predicates = [HasKL] in {
19-
let Uses = [XMM0, EAX], Defs = [EFLAGS] in {
21+
multiclass Aesencdec<string suffix> {
22+
def AESENC128KL#suffix : I<0xDC, MRMSrcMem, (outs VR128:$dst),
23+
(ins VR128:$src1, opaquemem:$src2),
24+
"aesenc128kl\t{$src2, $src1|$src1, $src2}",
25+
[(set VR128:$dst, EFLAGS, (X86aesenc128kl VR128:$src1, addr:$src2))]>,
26+
NoCD8, XS;
27+
def AESDEC128KL#suffix : I<0xDD, MRMSrcMem, (outs VR128:$dst),
28+
(ins VR128:$src1, opaquemem:$src2),
29+
"aesdec128kl\t{$src2, $src1|$src1, $src2}",
30+
[(set VR128:$dst, EFLAGS, (X86aesdec128kl VR128:$src1, addr:$src2))]>,
31+
NoCD8, XS;
32+
def AESENC256KL#suffix : I<0xDE, MRMSrcMem, (outs VR128:$dst),
33+
(ins VR128:$src1, opaquemem:$src2),
34+
"aesenc256kl\t{$src2, $src1|$src1, $src2}",
35+
[(set VR128:$dst, EFLAGS, (X86aesenc256kl VR128:$src1, addr:$src2))]>,
36+
NoCD8, XS;
37+
def AESDEC256KL#suffix : I<0xDF, MRMSrcMem, (outs VR128:$dst),
38+
(ins VR128:$src1, opaquemem:$src2),
39+
"aesdec256kl\t{$src2, $src1|$src1, $src2}",
40+
[(set VR128:$dst, EFLAGS, (X86aesdec256kl VR128:$src1, addr:$src2))]>,
41+
NoCD8, XS;
42+
}
43+
44+
let SchedRW = [WriteSystem] in {
45+
let Uses = [XMM0, EAX], Defs = [EFLAGS], Predicates = [HasKL] in {
2046
def LOADIWKEY : I<0xDC, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
2147
"loadiwkey\t{$src2, $src1|$src1, $src2}",
2248
[(int_x86_loadiwkey XMM0, VR128:$src1, VR128:$src2, EAX)]>, T8, XS;
2349
}
2450

25-
let Uses = [XMM0], Defs = [XMM0, XMM1, XMM2, XMM4, XMM5, XMM6, EFLAGS] in {
26-
def ENCODEKEY128 : I<0xFA, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
27-
"encodekey128\t{$src, $dst|$dst, $src}", []>, T8, XS;
28-
}
51+
let Predicates = [HasKL, NoEGPR] in {
52+
let Uses = [XMM0], Defs = [XMM0, XMM1, XMM2, XMM4, XMM5, XMM6, EFLAGS] in
53+
def ENCODEKEY128 : Encodekey<0xFA, "encodekey128">, T8;
2954

30-
let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in {
31-
def ENCODEKEY256 : I<0xFB, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
32-
"encodekey256\t{$src, $dst|$dst, $src}", []>, T8, XS;
33-
}
55+
let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in
56+
def ENCODEKEY256 : Encodekey<0xFB, "encodekey256">, T8;
3457

35-
let Constraints = "$src1 = $dst",
36-
Defs = [EFLAGS] in {
37-
def AESENC128KL : I<0xDC, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
38-
"aesenc128kl\t{$src2, $src1|$src1, $src2}",
39-
[(set VR128:$dst, EFLAGS,
40-
(X86aesenc128kl VR128:$src1, addr:$src2))]>, T8, XS;
58+
let Constraints = "$src1 = $dst", Defs = [EFLAGS] in
59+
defm "" : Aesencdec<"">, T8;
60+
}
4161

42-
def AESDEC128KL : I<0xDD, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
43-
"aesdec128kl\t{$src2, $src1|$src1, $src2}",
44-
[(set VR128:$dst, EFLAGS,
45-
(X86aesdec128kl VR128:$src1, addr:$src2))]>, T8, XS;
62+
let Predicates = [HasKL, HasEGPR, In64BitMode] in {
63+
let Uses = [XMM0], Defs = [XMM0, XMM1, XMM2, XMM4, XMM5, XMM6, EFLAGS] in
64+
def ENCODEKEY128_EVEX : Encodekey<0xDA, "encodekey128">, EVEX, T_MAP4;
4665

47-
def AESENC256KL : I<0xDE, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
48-
"aesenc256kl\t{$src2, $src1|$src1, $src2}",
49-
[(set VR128:$dst, EFLAGS,
50-
(X86aesenc256kl VR128:$src1, addr:$src2))]>, T8, XS;
66+
let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in
67+
def ENCODEKEY256_EVEX : Encodekey<0xDB, "encodekey256">, EVEX, T_MAP4;
5168

52-
def AESDEC256KL : I<0xDF, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
53-
"aesdec256kl\t{$src2, $src1|$src1, $src2}",
54-
[(set VR128:$dst, EFLAGS,
55-
(X86aesdec256kl VR128:$src1, addr:$src2))]>, T8, XS;
69+
let Constraints = "$src1 = $dst", Defs = [EFLAGS] in
70+
defm "" : Aesencdec<"_EVEX">, EVEX, T_MAP4;
5671
}
72+
} // SchedRW
5773

58-
} // SchedRW, Predicates
74+
multiclass Aesencdecwide<string suffix> {
75+
def AESENCWIDE128KL#suffix : I<0xD8, MRM0m, (outs), (ins opaquemem:$src), "aesencwide128kl\t$src", []>, NoCD8, XS;
76+
def AESDECWIDE128KL#suffix : I<0xD8, MRM1m, (outs), (ins opaquemem:$src), "aesdecwide128kl\t$src", []>, NoCD8, XS;
77+
def AESENCWIDE256KL#suffix : I<0xD8, MRM2m, (outs), (ins opaquemem:$src), "aesencwide256kl\t$src", []>, NoCD8, XS;
78+
def AESDECWIDE256KL#suffix : I<0xD8, MRM3m, (outs), (ins opaquemem:$src), "aesdecwide256kl\t$src", []>, NoCD8, XS;
79+
}
5980

60-
let SchedRW = [WriteSystem], Predicates = [HasWIDEKL] in {
61-
let Uses = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
62-
Defs = [EFLAGS, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
63-
mayLoad = 1 in {
64-
def AESENCWIDE128KL : I<0xD8, MRM0m, (outs), (ins opaquemem:$src),
65-
"aesencwide128kl\t$src", []>, T8, XS;
66-
def AESDECWIDE128KL : I<0xD8, MRM1m, (outs), (ins opaquemem:$src),
67-
"aesdecwide128kl\t$src", []>, T8, XS;
68-
def AESENCWIDE256KL : I<0xD8, MRM2m, (outs), (ins opaquemem:$src),
69-
"aesencwide256kl\t$src", []>, T8, XS;
70-
def AESDECWIDE256KL : I<0xD8, MRM3m, (outs), (ins opaquemem:$src),
71-
"aesdecwide256kl\t$src", []>, T8, XS;
72-
}
81+
let SchedRW = [WriteSystem], Uses = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
82+
Defs = [EFLAGS, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7], mayLoad = 1 in {
83+
let Predicates = [HasWIDEKL, NoEGPR] in
84+
defm "" : Aesencdecwide<"">, T8;
7385

74-
} // SchedRW, Predicates
86+
let Predicates = [HasWIDEKL, HasEGPR, In64BitMode] in
87+
defm "" : Aesencdecwide<"_EVEX">, EVEX, T_MAP4;
88+
} // SchedRW

‎llvm/lib/Target/X86/X86InstrMisc.td

Lines changed: 29 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -1557,32 +1557,39 @@ def MOVDIR64B64_EVEX : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$
15571557
//===----------------------------------------------------------------------===//
15581558
// ENQCMD/S - Enqueue 64-byte command as user with 64-byte write atomicity
15591559
//
1560+
multiclass Enqcmds<string suffix> {
1561+
def ENQCMD32#suffix : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src),
1562+
"enqcmd\t{$src, $dst|$dst, $src}",
1563+
[(set EFLAGS, (X86enqcmd GR32:$dst, addr:$src))]>,
1564+
NoCD8, XD, AdSize32;
1565+
def ENQCMD64#suffix : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
1566+
"enqcmd\t{$src, $dst|$dst, $src}",
1567+
[(set EFLAGS, (X86enqcmd GR64:$dst, addr:$src))]>,
1568+
NoCD8, XD, AdSize64;
1569+
1570+
def ENQCMDS32#suffix : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src),
1571+
"enqcmds\t{$src, $dst|$dst, $src}",
1572+
[(set EFLAGS, (X86enqcmds GR32:$dst, addr:$src))]>,
1573+
NoCD8, XS, AdSize32;
1574+
def ENQCMDS64#suffix : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
1575+
"enqcmds\t{$src, $dst|$dst, $src}",
1576+
[(set EFLAGS, (X86enqcmds GR64:$dst, addr:$src))]>,
1577+
NoCD8, XS, AdSize64;
1578+
}
1579+
15601580
let SchedRW = [WriteStore], Defs = [EFLAGS] in {
15611581
def ENQCMD16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem_GR16:$src),
1562-
"enqcmd\t{$src, $dst|$dst, $src}",
1563-
[(set EFLAGS, (X86enqcmd GR16:$dst, addr:$src))]>,
1582+
"enqcmd\t{$src, $dst|$dst, $src}",
1583+
[(set EFLAGS, (X86enqcmd GR16:$dst, addr:$src))]>,
15641584
T8, XD, AdSize16, Requires<[HasENQCMD, Not64BitMode]>;
1565-
def ENQCMD32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src),
1566-
"enqcmd\t{$src, $dst|$dst, $src}",
1567-
[(set EFLAGS, (X86enqcmd GR32:$dst, addr:$src))]>,
1568-
T8, XD, AdSize32, Requires<[HasENQCMD]>;
1569-
def ENQCMD64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
1570-
"enqcmd\t{$src, $dst|$dst, $src}",
1571-
[(set EFLAGS, (X86enqcmd GR64:$dst, addr:$src))]>,
1572-
T8, XD, AdSize64, Requires<[HasENQCMD, In64BitMode]>;
1573-
15741585
def ENQCMDS16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem_GR16:$src),
1575-
"enqcmds\t{$src, $dst|$dst, $src}",
1576-
[(set EFLAGS, (X86enqcmds GR16:$dst, addr:$src))]>,
1577-
T8, XS, AdSize16, Requires<[HasENQCMD, Not64BitMode]>;
1578-
def ENQCMDS32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src),
1579-
"enqcmds\t{$src, $dst|$dst, $src}",
1580-
[(set EFLAGS, (X86enqcmds GR32:$dst, addr:$src))]>,
1581-
T8, XS, AdSize32, Requires<[HasENQCMD]>;
1582-
def ENQCMDS64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
1583-
"enqcmds\t{$src, $dst|$dst, $src}",
1584-
[(set EFLAGS, (X86enqcmds GR64:$dst, addr:$src))]>,
1585-
T8, XS, AdSize64, Requires<[HasENQCMD, In64BitMode]>;
1586+
"enqcmds\t{$src, $dst|$dst, $src}",
1587+
[(set EFLAGS, (X86enqcmds GR16:$dst, addr:$src))]>,
1588+
T8, XS, AdSize16, Requires<[HasENQCMD, Not64BitMode]>;
1589+
1590+
defm "" : Enqcmds<"">, T8, Requires<[HasENQCMD, NoEGPR]>;
1591+
defm "" : Enqcmds<"_EVEX">, EVEX, T_MAP4, Requires<[HasENQCMD, HasEGPR, In64BitMode]>;
1592+
15861593
}
15871594

15881595
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/X86/X86InstrSystem.td

Lines changed: 27 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -436,22 +436,35 @@ def WRMSRLIST : I<0x01, MRM_C6, (outs), (ins), "wrmsrlist", []>, TB, XS;
436436
def RDMSRLIST : I<0x01, MRM_C6, (outs), (ins), "rdmsrlist", []>, TB, XD;
437437
}
438438

439-
let Predicates = [HasUSERMSR], mayLoad = 1 in {
440-
def URDMSRrr : I<0xf8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
441-
"urdmsr\t{$src, $dst|$dst, $src}",
442-
[(set GR64:$dst, (int_x86_urdmsr GR64:$src))]>, T8, XD;
443-
def URDMSRri : Ii32<0xf8, MRM0r, (outs GR64:$dst), (ins i64i32imm:$imm),
444-
"urdmsr\t{$imm, $dst|$dst, $imm}",
445-
[(set GR64:$dst, (int_x86_urdmsr i64immSExt32_su:$imm))]>, T_MAP7, XD, VEX;
439+
multiclass Urdwrmsr<Map rrmap, string suffix> {
440+
let mayLoad = 1 in {
441+
let OpMap = rrmap in
442+
def URDMSRrr#suffix : I<0xf8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
443+
"urdmsr\t{$src, $dst|$dst, $src}",
444+
[(set GR64:$dst, (int_x86_urdmsr GR64:$src))]>, XD, NoCD8;
445+
def URDMSRri#suffix : Ii32<0xf8, MRM0r, (outs GR64:$dst), (ins i64i32imm:$imm),
446+
"urdmsr\t{$imm, $dst|$dst, $imm}",
447+
[(set GR64:$dst, (int_x86_urdmsr i64immSExt32_su:$imm))]>,
448+
T_MAP7, VEX, XD, NoCD8;
446449
}
447-
let Predicates = [HasUSERMSR], mayStore = 1 in {
448-
def UWRMSRrr : I<0xf8, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
449-
"uwrmsr\t{$src2, $src1|$src1, $src2}",
450-
[(int_x86_uwrmsr GR64:$src1, GR64:$src2)]>, T8, XS;
451-
def UWRMSRir : Ii32<0xf8, MRM0r, (outs), (ins GR64:$src, i64i32imm:$imm),
452-
"uwrmsr\t{$src, $imm|$imm, $src}",
453-
[(int_x86_uwrmsr i64immSExt32_su:$imm, GR64:$src)]>, T_MAP7, XS, VEX;
450+
let mayStore = 1 in {
451+
let OpMap = rrmap in
452+
def UWRMSRrr#suffix : I<0xf8, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
453+
"uwrmsr\t{$src2, $src1|$src1, $src2}",
454+
[(int_x86_uwrmsr GR64:$src1, GR64:$src2)]>, XS, NoCD8;
455+
def UWRMSRir#suffix : Ii32<0xf8, MRM0r, (outs), (ins GR64:$src, i64i32imm:$imm),
456+
"uwrmsr\t{$src, $imm|$imm, $src}",
457+
[(int_x86_uwrmsr i64immSExt32_su:$imm, GR64:$src)]>,
458+
T_MAP7, VEX, XS, NoCD8;
459+
}
454460
}
461+
462+
let Predicates = [HasUSERMSR, NoEGPR] in
463+
defm "" : Urdwrmsr<T8, "">;
464+
465+
let Predicates = [HasUSERMSR, HasEGPR, In64BitMode] in
466+
defm "" : Urdwrmsr<T_MAP4, "_EVEX">, EVEX;
467+
455468
let Defs = [RAX, RDX], Uses = [ECX] in
456469
def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
457470

‎llvm/test/CodeGen/X86/enqcmd-intrinsics.ll

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@
22
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+enqcmd | FileCheck %s --check-prefix=X64
33
; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+enqcmd | FileCheck %s --check-prefix=X86
44
; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -mattr=+enqcmd | FileCheck %s --check-prefix=X32
5+
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+enqcmd,+egpr --show-mc-encoding | FileCheck %s --check-prefix=EGPR
56

67
define i8 @test_enqcmd(ptr %dst, ptr %src) {
78
; X64-LABEL: test_enqcmd:
@@ -23,6 +24,12 @@ define i8 @test_enqcmd(ptr %dst, ptr %src) {
2324
; X32-NEXT: enqcmd (%esi), %edi
2425
; X32-NEXT: sete %al
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; X32-NEXT: retq
27+
;
28+
; EGPR-LABEL: test_enqcmd:
29+
; EGPR: # %bb.0: # %entry
30+
; EGPR-NEXT: enqcmd (%rsi), %rdi # EVEX TO LEGACY Compression encoding: [0xf2,0x0f,0x38,0xf8,0x3e]
31+
; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
32+
; EGPR-NEXT: retq # encoding: [0xc3]
2633
entry:
2734

2835

@@ -50,6 +57,12 @@ define i8 @test_enqcmds(ptr %dst, ptr %src) {
5057
; X32-NEXT: enqcmds (%esi), %edi
5158
; X32-NEXT: sete %al
5259
; X32-NEXT: retq
60+
;
61+
; EGPR-LABEL: test_enqcmds:
62+
; EGPR: # %bb.0: # %entry
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; EGPR-NEXT: enqcmds (%rsi), %rdi # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xf8,0x3e]
64+
; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
65+
; EGPR-NEXT: retq # encoding: [0xc3]
5366
entry:
5467

5568

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