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[RISCV] Add tests for combineBinOpOfZExts. NFC (#86689)
Unlike add, sub and mul, we don't have widening instructions for div, rem and logical ops, so we don't have any test coverage if we were to extend combineBinOpOfZExts to handle them. Adding tests coincidentally revealed that logical ops are already narrowed as a generic DAG combine via DAGCombiner::hoistLogicOpWithSameOpcodeHands. So we don't actually need to run combineBinOpOfZExts on them.
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‎llvm/test/CodeGen/RISCV/rvv/binop-zext.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
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; Check that we perform binary arithmetic in a narrower type where possible, via
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; combineBinOpOfZExt or otherwise.
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define <vscale x 8 x i32> @add(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
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; CHECK-LABEL: add:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
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; CHECK-NEXT: vwaddu.vv v12, v8, v9
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; CHECK-NEXT: vzext.vf2 v8, v12
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; CHECK-NEXT: ret
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%a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>
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%b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>
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%add = add <vscale x 8 x i32> %a.zext, %b.zext
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ret <vscale x 8 x i32> %add
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}
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define <vscale x 8 x i32> @sub(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
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; CHECK-LABEL: sub:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
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; CHECK-NEXT: vwsubu.vv v12, v8, v9
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; CHECK-NEXT: vsext.vf2 v8, v12
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; CHECK-NEXT: ret
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%a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>
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%b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>
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%sub = sub <vscale x 8 x i32> %a.zext, %b.zext
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ret <vscale x 8 x i32> %sub
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}
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define <vscale x 8 x i32> @mul(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
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; CHECK-LABEL: mul:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
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; CHECK-NEXT: vwmulu.vv v12, v8, v9
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; CHECK-NEXT: vzext.vf2 v8, v12
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; CHECK-NEXT: ret
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%a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>
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%b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>
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%mul = mul <vscale x 8 x i32> %a.zext, %b.zext
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ret <vscale x 8 x i32> %mul
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}
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define <vscale x 8 x i32> @sdiv(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
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; CHECK-LABEL: sdiv:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
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; CHECK-NEXT: vzext.vf4 v12, v8
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; CHECK-NEXT: vzext.vf4 v16, v9
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; CHECK-NEXT: vdivu.vv v8, v12, v16
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; CHECK-NEXT: ret
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%a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>
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%b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>
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%sdiv = sdiv <vscale x 8 x i32> %a.zext, %b.zext
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ret <vscale x 8 x i32> %sdiv
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}
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define <vscale x 8 x i32> @udiv(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
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; CHECK-LABEL: udiv:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
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; CHECK-NEXT: vzext.vf4 v12, v8
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; CHECK-NEXT: vzext.vf4 v16, v9
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; CHECK-NEXT: vdivu.vv v8, v12, v16
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; CHECK-NEXT: ret
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%a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>
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%b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>
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%udiv = udiv <vscale x 8 x i32> %a.zext, %b.zext
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ret <vscale x 8 x i32> %udiv
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}
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define <vscale x 8 x i32> @srem(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
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; CHECK-LABEL: srem:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
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; CHECK-NEXT: vzext.vf4 v12, v8
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; CHECK-NEXT: vzext.vf4 v16, v9
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; CHECK-NEXT: vremu.vv v8, v12, v16
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; CHECK-NEXT: ret
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%a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>
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%b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>
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%srem = srem <vscale x 8 x i32> %a.zext, %b.zext
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ret <vscale x 8 x i32> %srem
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}
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define <vscale x 8 x i32> @urem(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
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; CHECK-LABEL: urem:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
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; CHECK-NEXT: vzext.vf4 v12, v8
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; CHECK-NEXT: vzext.vf4 v16, v9
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; CHECK-NEXT: vremu.vv v8, v12, v16
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; CHECK-NEXT: ret
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%a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>
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%b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>
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%urem = urem <vscale x 8 x i32> %a.zext, %b.zext
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ret <vscale x 8 x i32> %urem
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}
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define <vscale x 8 x i32> @and(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
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; CHECK-LABEL: and:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
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; CHECK-NEXT: vand.vv v12, v8, v9
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; CHECK-NEXT: vzext.vf4 v8, v12
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; CHECK-NEXT: ret
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%a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>
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%b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>
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%shl = and <vscale x 8 x i32> %a.zext, %b.zext
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ret <vscale x 8 x i32> %shl
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}
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define <vscale x 8 x i32> @or(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
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; CHECK-LABEL: or:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
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; CHECK-NEXT: vor.vv v12, v8, v9
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; CHECK-NEXT: vzext.vf4 v8, v12
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; CHECK-NEXT: ret
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%a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>
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%b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>
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%or = or <vscale x 8 x i32> %a.zext, %b.zext
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ret <vscale x 8 x i32> %or
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}
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define <vscale x 8 x i32> @xor(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
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; CHECK-LABEL: xor:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
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; CHECK-NEXT: vxor.vv v12, v8, v9
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; CHECK-NEXT: vzext.vf4 v8, v12
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; CHECK-NEXT: ret
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%a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>
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%b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>
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%xor = xor <vscale x 8 x i32> %a.zext, %b.zext
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ret <vscale x 8 x i32> %xor
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}

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