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[X86][NFC] Set default OpPrefix to PS for XOP/VEX/EVEX instructions
It helps simplify the class definitions. Now, the only explicit usage of PS is to check prefix 0x66/0xf2/0xf3 can not be used a prefix, e.g. wbinvd. See 82974e0 for more details.
1 parent 0e07bf9 commit 6e20df1

14 files changed

+247
-246
lines changed

‎llvm/lib/Target/X86/X86InstrAMX.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ let Predicates = [HasAMXTILE, In64BitMode] in {
2020
Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
2121
def LDTILECFG : I <0x49, MRM0m, (outs), (ins opaquemem:$src),
2222
"ldtilecfg\t$src",
23-
[(int_x86_ldtilecfg addr:$src)]>, VEX, T8, PS;
23+
[(int_x86_ldtilecfg addr:$src)]>, VEX, T8;
2424
let hasSideEffects = 1 in
2525
def STTILECFG : I <0x49, MRM0m, (outs), (ins opaquemem:$src),
2626
"sttilecfg\t$src",
@@ -37,7 +37,7 @@ let Predicates = [HasAMXTILE, In64BitMode] in {
3737
VEX, T8, PD;
3838
let Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
3939
def TILERELEASE : I<0x49, MRM_C0, (outs), (ins),
40-
"tilerelease", [(int_x86_tilerelease)]>, VEX, T8, PS;
40+
"tilerelease", [(int_x86_tilerelease)]>, VEX, T8;
4141
let mayStore = 1 in
4242
def TILESTORED : I<0x4b, MRMDestMemFSIB, (outs),
4343
(ins sibmem:$dst, TILE:$src),
@@ -103,7 +103,7 @@ let Predicates = [HasAMXINT8, In64BitMode] in {
103103
def TDPBUUD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
104104
(ins TILE:$src1, TILE:$src2, TILE:$src3),
105105
"tdpbuud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
106-
VEX, VVVV, T8, PS;
106+
VEX, VVVV, T8;
107107
}
108108

109109
// Pseduo instruction for RA.
@@ -226,7 +226,7 @@ let Predicates = [HasAMXCOMPLEX, In64BitMode] in {
226226
def TCMMRLFP16PS : I<0x6c, MRMSrcReg4VOp3, (outs TILE:$dst),
227227
(ins TILE:$src1, TILE:$src2, TILE:$src3),
228228
"tcmmrlfp16ps\t{$src3, $src2, $src1|$src1, $src2, $src3}",
229-
[]>, VEX, VVVV, WIG, T8, PS;
229+
[]>, VEX, VVVV, WIG, T8;
230230

231231
} // Constraints = "$src1 = $dst"
232232

‎llvm/lib/Target/X86/X86InstrAVX512.td

Lines changed: 64 additions & 64 deletions
Large diffs are not rendered by default.

‎llvm/lib/Target/X86/X86InstrArithmetic.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1117,8 +1117,8 @@ let Predicates = [HasBMI, HasEGPR, In64BitMode] in {
11171117

11181118
// Complexity is reduced to give and with immediate a chance to match first.
11191119
let Defs = [EFLAGS], AddedComplexity = -6 in {
1120-
defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32, WriteALU>, T8, PS;
1121-
defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64, WriteALU>, T8, PS, REX_W;
1120+
defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32, WriteALU>, T8;
1121+
defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64, WriteALU>, T8, REX_W;
11221122
}
11231123

11241124
let Predicates = [HasBMI], AddedComplexity = -6 in {

‎llvm/lib/Target/X86/X86InstrFPStack.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -666,20 +666,20 @@ def FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", []>;
666666

667667
let Uses = [FPSW, FPCW] in {
668668
def FXSAVE : I<0xAE, MRM0m, (outs), (ins opaquemem:$dst),
669-
"fxsave\t$dst", [(int_x86_fxsave addr:$dst)]>, TB, PS,
669+
"fxsave\t$dst", [(int_x86_fxsave addr:$dst)]>, TB,
670670
Requires<[HasFXSR]>;
671671
def FXSAVE64 : RI<0xAE, MRM0m, (outs), (ins opaquemem:$dst),
672672
"fxsave64\t$dst", [(int_x86_fxsave64 addr:$dst)]>,
673-
TB, PS, Requires<[HasFXSR, In64BitMode]>;
673+
TB, Requires<[HasFXSR, In64BitMode]>;
674674
} // Uses = [FPSW, FPCW]
675675

676676
let Defs = [FPSW, FPCW] in {
677677
def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaquemem:$src),
678678
"fxrstor\t$src", [(int_x86_fxrstor addr:$src)]>,
679-
TB, PS, Requires<[HasFXSR]>;
679+
TB, Requires<[HasFXSR]>;
680680
def FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaquemem:$src),
681681
"fxrstor64\t$src", [(int_x86_fxrstor64 addr:$src)]>,
682-
TB, PS, Requires<[HasFXSR, In64BitMode]>;
682+
TB, Requires<[HasFXSR, In64BitMode]>;
683683
} // Defs = [FPSW, FPCW]
684684
} // SchedRW
685685

‎llvm/lib/Target/X86/X86InstrFormats.td

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -234,7 +234,9 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
234234
// based on address size of the mode?
235235
bits<2> AdSizeBits = AdSize.Value;
236236

237-
Prefix OpPrefix = NoPrfx; // Which prefix byte does this inst have?
237+
Encoding OpEnc = EncNormal; // Encoding used by this instruction
238+
// Which prefix byte does this inst have?
239+
Prefix OpPrefix = !if(!eq(OpEnc, EncNormal), NoPrfx, PS);
238240
bits<3> OpPrefixBits = OpPrefix.Value;
239241
Map OpMap = OB; // Which opcode map does this inst have?
240242
bits<4> OpMapBits = OpMap.Value;
@@ -243,7 +245,6 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
243245
bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
244246
Domain ExeDomain = d;
245247
bit hasREPPrefix = 0; // Does this inst have a REP prefix?
246-
Encoding OpEnc = EncNormal; // Encoding used by this instruction
247248
bits<2> OpEncBits = OpEnc.Value;
248249
bit IgnoresW = 0; // Does this inst ignore REX_W field?
249250
bit EVEX_W1_VEX_W0 = 0; // This EVEX inst with VEX.W==1 can become a VEX

‎llvm/lib/Target/X86/X86InstrMMX.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -487,13 +487,13 @@ def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
487487
// -- Conversion Instructions
488488
defm MMX_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
489489
f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}",
490-
WriteCvtPS2I, SSEPackedSingle>, TB, PS, SIMD_EXC;
490+
WriteCvtPS2I, SSEPackedSingle>, TB, SIMD_EXC;
491491
defm MMX_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
492492
f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
493493
WriteCvtPD2I, SSEPackedDouble>, TB, PD, SIMD_EXC;
494494
defm MMX_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
495495
f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}",
496-
WriteCvtPS2I, SSEPackedSingle>, TB, PS, SIMD_EXC;
496+
WriteCvtPS2I, SSEPackedSingle>, TB, SIMD_EXC;
497497
defm MMX_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
498498
f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
499499
WriteCvtPD2I, SSEPackedDouble>, TB, PD, SIMD_EXC;
@@ -504,7 +504,7 @@ let Constraints = "$src1 = $dst" in {
504504
defm MMX_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
505505
int_x86_sse_cvtpi2ps,
506506
i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
507-
SSEPackedSingle>, TB, PS, SIMD_EXC;
507+
SSEPackedSingle>, TB, SIMD_EXC;
508508
}
509509

510510
// Extract / Insert

‎llvm/lib/Target/X86/X86InstrMisc.td

Lines changed: 41 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -165,10 +165,10 @@ def POPP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "popp\t$reg", []>,
165165
REX_W, ExplicitREX2Prefix, Requires<[In64BitMode]>;
166166
def POP2: I<0x8F, MRM0r, (outs GR64:$reg1, GR64:$reg2), (ins),
167167
"pop2\t{$reg2, $reg1|$reg1, $reg2}",
168-
[]>, EVEX, VVVV, EVEX_B, T_MAP4, PS;
168+
[]>, EVEX, VVVV, EVEX_B, T_MAP4;
169169
def POP2P: I<0x8F, MRM0r, (outs GR64:$reg1, GR64:$reg2), (ins),
170170
"pop2p\t{$reg2, $reg1|$reg1, $reg2}",
171-
[]>, EVEX, VVVV, EVEX_B, T_MAP4, PS, REX_W;
171+
[]>, EVEX, VVVV, EVEX_B, T_MAP4, REX_W;
172172

173173
} // mayLoad, SchedRW
174174
let mayLoad = 1, mayStore = 1, SchedRW = [WriteCopy] in
@@ -186,10 +186,10 @@ def PUSHP64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "pushp\t$reg", []>,
186186
REX_W, ExplicitREX2Prefix, Requires<[In64BitMode]>;
187187
def PUSH2: I<0xFF, MRM6r, (outs), (ins GR64:$reg1, GR64:$reg2),
188188
"push2\t{$reg2, $reg1|$reg1, $reg2}",
189-
[]>, EVEX, VVVV, EVEX_B, T_MAP4, PS;
189+
[]>, EVEX, VVVV, EVEX_B, T_MAP4;
190190
def PUSH2P: I<0xFF, MRM6r, (outs), (ins GR64:$reg1, GR64:$reg2),
191191
"push2p\t{$reg2, $reg1|$reg1, $reg2}",
192-
[]>, EVEX, VVVV, EVEX_B, T_MAP4, PS, REX_W;
192+
[]>, EVEX, VVVV, EVEX_B, T_MAP4, REX_W;
193193
} // mayStore, SchedRW
194194
let mayLoad = 1, mayStore = 1, SchedRW = [WriteCopy] in {
195195
def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>,
@@ -251,52 +251,52 @@ let Defs = [EFLAGS] in {
251251
def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
252252
"bsf{w}\t{$src, $dst|$dst, $src}",
253253
[(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>,
254-
TB, PS, OpSize16, Sched<[WriteBSF]>;
254+
TB, OpSize16, Sched<[WriteBSF]>;
255255
def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
256256
"bsf{w}\t{$src, $dst|$dst, $src}",
257257
[(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>,
258-
TB, PS, OpSize16, Sched<[WriteBSFLd]>;
258+
TB, OpSize16, Sched<[WriteBSFLd]>;
259259
def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
260260
"bsf{l}\t{$src, $dst|$dst, $src}",
261261
[(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>,
262-
TB, PS, OpSize32, Sched<[WriteBSF]>;
262+
TB, OpSize32, Sched<[WriteBSF]>;
263263
def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
264264
"bsf{l}\t{$src, $dst|$dst, $src}",
265265
[(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>,
266-
TB, PS, OpSize32, Sched<[WriteBSFLd]>;
266+
TB, OpSize32, Sched<[WriteBSFLd]>;
267267
def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
268268
"bsf{q}\t{$src, $dst|$dst, $src}",
269269
[(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>,
270-
TB, PS, Sched<[WriteBSF]>;
270+
TB, Sched<[WriteBSF]>;
271271
def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
272272
"bsf{q}\t{$src, $dst|$dst, $src}",
273273
[(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>,
274-
TB, PS, Sched<[WriteBSFLd]>;
274+
TB, Sched<[WriteBSFLd]>;
275275

276276
def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
277277
"bsr{w}\t{$src, $dst|$dst, $src}",
278278
[(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>,
279-
TB, PS, OpSize16, Sched<[WriteBSR]>;
279+
TB, OpSize16, Sched<[WriteBSR]>;
280280
def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
281281
"bsr{w}\t{$src, $dst|$dst, $src}",
282282
[(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>,
283-
TB, PS, OpSize16, Sched<[WriteBSRLd]>;
283+
TB, OpSize16, Sched<[WriteBSRLd]>;
284284
def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
285285
"bsr{l}\t{$src, $dst|$dst, $src}",
286286
[(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>,
287-
TB, PS, OpSize32, Sched<[WriteBSR]>;
287+
TB, OpSize32, Sched<[WriteBSR]>;
288288
def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
289289
"bsr{l}\t{$src, $dst|$dst, $src}",
290290
[(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>,
291-
TB, PS, OpSize32, Sched<[WriteBSRLd]>;
291+
TB, OpSize32, Sched<[WriteBSRLd]>;
292292
def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
293293
"bsr{q}\t{$src, $dst|$dst, $src}",
294294
[(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>,
295-
TB, PS, Sched<[WriteBSR]>;
295+
TB, Sched<[WriteBSR]>;
296296
def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
297297
"bsr{q}\t{$src, $dst|$dst, $src}",
298298
[(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>,
299-
TB, PS, Sched<[WriteBSRLd]>;
299+
TB, Sched<[WriteBSRLd]>;
300300
} // Defs = [EFLAGS]
301301

302302
let SchedRW = [WriteMicrocoded] in {
@@ -1095,29 +1095,29 @@ let Predicates = [HasMOVBE] in {
10951095
def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
10961096
"movbe{w}\t{$src, $dst|$dst, $src}",
10971097
[(set GR16:$dst, (bswap (loadi16 addr:$src)))]>,
1098-
OpSize16, T8, PS;
1098+
OpSize16, T8;
10991099
def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
11001100
"movbe{l}\t{$src, $dst|$dst, $src}",
11011101
[(set GR32:$dst, (bswap (loadi32 addr:$src)))]>,
1102-
OpSize32, T8, PS;
1102+
OpSize32, T8;
11031103
def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
11041104
"movbe{q}\t{$src, $dst|$dst, $src}",
11051105
[(set GR64:$dst, (bswap (loadi64 addr:$src)))]>,
1106-
T8, PS;
1106+
T8;
11071107
}
11081108
let SchedRW = [WriteStore] in {
11091109
def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
11101110
"movbe{w}\t{$src, $dst|$dst, $src}",
11111111
[(store (bswap GR16:$src), addr:$dst)]>,
1112-
OpSize16, T8, PS;
1112+
OpSize16, T8;
11131113
def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
11141114
"movbe{l}\t{$src, $dst|$dst, $src}",
11151115
[(store (bswap GR32:$src), addr:$dst)]>,
1116-
OpSize32, T8, PS;
1116+
OpSize32, T8;
11171117
def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
11181118
"movbe{q}\t{$src, $dst|$dst, $src}",
11191119
[(store (bswap GR64:$src), addr:$dst)]>,
1120-
T8, PS;
1120+
T8;
11211121
}
11221122
}
11231123

@@ -1127,25 +1127,25 @@ let Predicates = [HasMOVBE] in {
11271127
let Predicates = [HasRDRAND], Defs = [EFLAGS], SchedRW = [WriteSystem] in {
11281128
def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
11291129
"rdrand{w}\t$dst", [(set GR16:$dst, EFLAGS, (X86rdrand))]>,
1130-
OpSize16, TB, PS;
1130+
OpSize16, TB;
11311131
def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
11321132
"rdrand{l}\t$dst", [(set GR32:$dst, EFLAGS, (X86rdrand))]>,
1133-
OpSize32, TB, PS;
1133+
OpSize32, TB;
11341134
def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
11351135
"rdrand{q}\t$dst", [(set GR64:$dst, EFLAGS, (X86rdrand))]>,
1136-
TB, PS;
1136+
TB;
11371137
}
11381138

11391139
//===----------------------------------------------------------------------===//
11401140
// RDSEED Instruction
11411141
//
11421142
let Predicates = [HasRDSEED], Defs = [EFLAGS], SchedRW = [WriteSystem] in {
11431143
def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins), "rdseed{w}\t$dst",
1144-
[(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB, PS;
1144+
[(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB;
11451145
def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins), "rdseed{l}\t$dst",
1146-
[(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, TB, PS;
1146+
[(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, TB;
11471147
def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdseed{q}\t$dst",
1148-
[(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB, PS;
1148+
[(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;
11491149
}
11501150

11511151
//===----------------------------------------------------------------------===//
@@ -1218,11 +1218,11 @@ multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
12181218
let hasSideEffects = 0 in {
12191219
def rr#Suffix : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
12201220
!strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>,
1221-
T8, PS, VEX, VVVV, Sched<[sched]>;
1221+
T8, VEX, VVVV, Sched<[sched]>;
12221222
let mayLoad = 1 in
12231223
def rm#Suffix : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
12241224
!strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>,
1225-
T8, PS, VEX, VVVV, Sched<[sched.Folded]>;
1225+
T8, VEX, VVVV, Sched<[sched.Folded]>;
12261226
}
12271227
}
12281228

@@ -1288,12 +1288,12 @@ multiclass bmi4VOp3_base<bits<8> opc, string mnemonic, RegisterClass RC,
12881288
def rr#Suffix : I<opc, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2),
12891289
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
12901290
[(set RC:$dst, (OpNode RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
1291-
T8, PS, VEX, Sched<[Sched]>;
1291+
T8, VEX, Sched<[Sched]>;
12921292
let mayLoad = 1 in
12931293
def rm#Suffix : I<opc, MRMSrcMem4VOp3, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
12941294
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
12951295
[(set RC:$dst, (OpNode (ld_frag addr:$src1), RC:$src2)),
1296-
(implicit EFLAGS)]>, T8, PS, VEX,
1296+
(implicit EFLAGS)]>, T8, VEX,
12971297
Sched<[Sched.Folded,
12981298
// x86memop:$src1
12991299
ReadDefault, ReadDefault, ReadDefault, ReadDefault,
@@ -1497,19 +1497,19 @@ let SchedRW = [WriteStore] in {
14971497
def MOVDIRI32 : I<0xF9, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
14981498
"movdiri\t{$src, $dst|$dst, $src}",
14991499
[(int_x86_directstore32 addr:$dst, GR32:$src)]>,
1500-
T8, PS, Requires<[HasMOVDIRI, NoEGPR]>;
1500+
T8, Requires<[HasMOVDIRI, NoEGPR]>;
15011501
def MOVDIRI64 : RI<0xF9, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
15021502
"movdiri\t{$src, $dst|$dst, $src}",
15031503
[(int_x86_directstore64 addr:$dst, GR64:$src)]>,
1504-
T8, PS, Requires<[In64BitMode, HasMOVDIRI, NoEGPR]>;
1504+
T8, Requires<[In64BitMode, HasMOVDIRI, NoEGPR]>;
15051505
def MOVDIRI32_EVEX : I<0xF9, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
15061506
"movdiri\t{$src, $dst|$dst, $src}",
15071507
[(int_x86_directstore32 addr:$dst, GR32:$src)]>,
1508-
EVEX, NoCD8, T_MAP4, PS, Requires<[In64BitMode, HasMOVDIRI, HasEGPR]>;
1508+
EVEX, NoCD8, T_MAP4, Requires<[In64BitMode, HasMOVDIRI, HasEGPR]>;
15091509
def MOVDIRI64_EVEX : RI<0xF9, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
15101510
"movdiri\t{$src, $dst|$dst, $src}",
15111511
[(int_x86_directstore64 addr:$dst, GR64:$src)]>,
1512-
EVEX, NoCD8, T_MAP4, PS, Requires<[In64BitMode, HasMOVDIRI, HasEGPR]>;
1512+
EVEX, NoCD8, T_MAP4, Requires<[In64BitMode, HasMOVDIRI, HasEGPR]>;
15131513
} // SchedRW
15141514

15151515
//===----------------------------------------------------------------------===//
@@ -1588,11 +1588,11 @@ let SchedRW = [WriteSystem] in {
15881588
let Uses = [EAX, EDX] in
15891589
def INVLPGB32 : I<0x01, MRM_FE, (outs), (ins),
15901590
"invlpgb", []>,
1591-
TB, PS, Requires<[Not64BitMode]>;
1591+
TB, Requires<[Not64BitMode]>;
15921592
let Uses = [RAX, EDX] in
15931593
def INVLPGB64 : I<0x01, MRM_FE, (outs), (ins),
15941594
"invlpgb", []>,
1595-
TB, PS, Requires<[In64BitMode]>;
1595+
TB, Requires<[In64BitMode]>;
15961596
} // SchedRW
15971597

15981598
//===----------------------------------------------------------------------===//
@@ -1602,7 +1602,7 @@ let SchedRW = [WriteSystem] in {
16021602
let SchedRW = [WriteSystem] in {
16031603
def TLBSYNC : I<0x01, MRM_FF, (outs), (ins),
16041604
"tlbsync", []>,
1605-
TB, PS, Requires<[]>;
1605+
TB, Requires<[]>;
16061606
} // SchedRW
16071607

16081608
//===----------------------------------------------------------------------===//
@@ -1617,7 +1617,7 @@ let Uses = [EAX], SchedRW = [WriteSystem] in
16171617
//
16181618
let SchedRW = [WriteSystem] in
16191619
def SERIALIZE : I<0x01, MRM_E8, (outs), (ins), "serialize",
1620-
[(int_x86_serialize)]>, TB, PS,
1620+
[(int_x86_serialize)]>, TB,
16211621
Requires<[HasSERIALIZE]>;
16221622

16231623
//===----------------------------------------------------------------------===//
@@ -1711,4 +1711,4 @@ def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src",
17111711

17121712
let Predicates = [HasCLDEMOTE], SchedRW = [WriteLoad] in
17131713
def CLDEMOTE : I<0x1C, MRM0m, (outs), (ins i8mem:$src), "cldemote\t$src",
1714-
[(int_x86_cldemote addr:$src)]>, TB, PS;
1714+
[(int_x86_cldemote addr:$src)]>, TB;

‎llvm/lib/Target/X86/X86InstrRAOINT.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ multiclass RAOINT_BASE<string OpcodeStr> {
3939
Sched<[WriteALURMW]>, REX_W;
4040
}
4141

42-
defm AADD : RAOINT_BASE<"add">, T8, PS;
42+
defm AADD : RAOINT_BASE<"add">, T8;
4343
defm AAND : RAOINT_BASE<"and">, T8, PD;
4444
defm AOR : RAOINT_BASE<"or" >, T8, XD;
4545
defm AXOR : RAOINT_BASE<"xor">, T8, XS;

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