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[AArch64] Emit fewer CFI instructions for synchronous unwind tables
The instruction-precise, or asynchronous, unwind tables usually take up much more space than the synchronous ones. If a user is concerned about the load size of the program and does not need the features provided with the asynchronous tables, the compiler should be able to generate the more compact variant. This patch changes the generation of CFI instructions for these cases so that they all come in one chunk in the prolog; it emits only one `.cfi_def_cfa*` instruction followed by `.cfi_offset` ones after all stack adjustments and register spills, and avoids generating CFI instructions in the epilog(s) as well as any other exceeding CFI instructions like `.cfi_remember_state` and `.cfi_restore_state`. Effectively, it reverses the effects of D111411 and D114545 on functions with the `uwtable(sync)` attribute. As a side effect, it also restores the behavior on functions that have neither `uwtable` nor `nounwind` attributes. Differential Revision: https://reviews.llvm.org/D153098
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‎llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

Lines changed: 53 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1364,6 +1364,27 @@ static void emitShadowCallStackEpilogue(const TargetInstrInfo &TII,
13641364
}
13651365
}
13661366

1367+
// Define the current CFA rule to use the provided FP.
1368+
static void emitDefineCFAWithFP(MachineFunction &MF, MachineBasicBlock &MBB,
1369+
MachineBasicBlock::iterator MBBI,
1370+
const DebugLoc &DL, unsigned FixedObject) {
1371+
const AArch64Subtarget &STI = MF.getSubtarget<AArch64Subtarget>();
1372+
const AArch64RegisterInfo *TRI = STI.getRegisterInfo();
1373+
const TargetInstrInfo *TII = STI.getInstrInfo();
1374+
AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
1375+
1376+
const int OffsetToFirstCalleeSaveFromFP =
1377+
AFI->getCalleeSaveBaseToFrameRecordOffset() -
1378+
AFI->getCalleeSavedStackSize();
1379+
Register FramePtr = TRI->getFrameRegister(MF);
1380+
unsigned Reg = TRI->getDwarfRegNum(FramePtr, true);
1381+
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
1382+
nullptr, Reg, FixedObject - OffsetToFirstCalleeSaveFromFP));
1383+
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
1384+
.addCFIIndex(CFIIndex)
1385+
.setMIFlags(MachineInstr::FrameSetup);
1386+
}
1387+
13671388
void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
13681389
MachineBasicBlock &MBB) const {
13691390
MachineBasicBlock::iterator MBBI = MBB.begin();
@@ -1375,6 +1396,7 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
13751396
MachineModuleInfo &MMI = MF.getMMI();
13761397
AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
13771398
bool EmitCFI = AFI->needsDwarfUnwindInfo(MF);
1399+
bool EmitAsyncCFI = AFI->needsAsyncDwarfUnwindInfo(MF);
13781400
bool HasFP = hasFP(MF);
13791401
bool NeedsWinCFI = needsWinCFI(MF);
13801402
bool HasWinCFI = false;
@@ -1535,15 +1557,15 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
15351557
emitFrameOffset(MBB, MBBI, DL, AArch64::SP, AArch64::SP,
15361558
StackOffset::getFixed(-NumBytes), TII,
15371559
MachineInstr::FrameSetup, false, NeedsWinCFI, &HasWinCFI,
1538-
EmitCFI);
1560+
EmitAsyncCFI);
15391561
NumBytes = 0;
15401562
} else if (HomPrologEpilog) {
15411563
// Stack has been already adjusted.
15421564
NumBytes -= PrologueSaveSize;
15431565
} else if (PrologueSaveSize != 0) {
15441566
MBBI = convertCalleeSaveRestoreToSPPrePostIncDec(
15451567
MBB, MBBI, DL, TII, -PrologueSaveSize, NeedsWinCFI, &HasWinCFI,
1546-
EmitCFI);
1568+
EmitAsyncCFI);
15471569
NumBytes -= PrologueSaveSize;
15481570
}
15491571
assert(NumBytes >= 0 && "Negative stack allocation size!?");
@@ -1604,25 +1626,14 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
16041626
NeedsWinCFI = false;
16051627
}
16061628
}
1607-
if (EmitCFI) {
1608-
// Define the current CFA rule to use the provided FP.
1609-
const int OffsetToFirstCalleeSaveFromFP =
1610-
AFI->getCalleeSaveBaseToFrameRecordOffset() -
1611-
AFI->getCalleeSavedStackSize();
1612-
Register FramePtr = RegInfo->getFrameRegister(MF);
1613-
unsigned Reg = RegInfo->getDwarfRegNum(FramePtr, true);
1614-
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
1615-
nullptr, Reg, FixedObject - OffsetToFirstCalleeSaveFromFP));
1616-
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
1617-
.addCFIIndex(CFIIndex)
1618-
.setMIFlags(MachineInstr::FrameSetup);
1619-
}
1629+
if (EmitAsyncCFI)
1630+
emitDefineCFAWithFP(MF, MBB, MBBI, DL, FixedObject);
16201631
}
16211632

16221633
// Now emit the moves for whatever callee saved regs we have (including FP,
16231634
// LR if those are saved). Frame instructions for SVE register are emitted
16241635
// later, after the instruction which actually save SVE regs.
1625-
if (EmitCFI)
1636+
if (EmitAsyncCFI)
16261637
emitCalleeSavedGPRLocations(MBB, MBBI);
16271638

16281639
// Alignment is required for the parent frame, not the funclet
@@ -1766,16 +1777,16 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
17661777
emitFrameOffset(
17671778
MBB, CalleeSavesBegin, DL, AArch64::SP, AArch64::SP, -AllocateBefore, TII,
17681779
MachineInstr::FrameSetup, false, false, nullptr,
1769-
EmitCFI && !HasFP && AllocateBefore,
1780+
EmitAsyncCFI && !HasFP && AllocateBefore,
17701781
StackOffset::getFixed((int64_t)MFI.getStackSize() - NumBytes));
17711782

1772-
if (EmitCFI)
1783+
if (EmitAsyncCFI)
17731784
emitCalleeSavedSVELocations(MBB, CalleeSavesEnd);
17741785

17751786
// Finally allocate remaining SVE stack space.
17761787
emitFrameOffset(MBB, CalleeSavesEnd, DL, AArch64::SP, AArch64::SP,
17771788
-AllocateAfter, TII, MachineInstr::FrameSetup, false, false,
1778-
nullptr, EmitCFI && !HasFP && AllocateAfter,
1789+
nullptr, EmitAsyncCFI && !HasFP && AllocateAfter,
17791790
AllocateBefore + StackOffset::getFixed(
17801791
(int64_t)MFI.getStackSize() - NumBytes));
17811792

@@ -1796,7 +1807,7 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
17961807
emitFrameOffset(
17971808
MBB, MBBI, DL, scratchSPReg, AArch64::SP,
17981809
StackOffset::getFixed(-NumBytes), TII, MachineInstr::FrameSetup,
1799-
false, NeedsWinCFI, &HasWinCFI, EmitCFI && !HasFP,
1810+
false, NeedsWinCFI, &HasWinCFI, EmitAsyncCFI && !HasFP,
18001811
SVEStackSize +
18011812
StackOffset::getFixed((int64_t)MFI.getStackSize() - NumBytes));
18021813
}
@@ -1858,6 +1869,23 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
18581869
MBB.addLiveIn(AArch64::X1);
18591870
}
18601871
}
1872+
1873+
if (EmitCFI && !EmitAsyncCFI) {
1874+
if (HasFP) {
1875+
emitDefineCFAWithFP(MF, MBB, MBBI, DL, FixedObject);
1876+
} else {
1877+
StackOffset TotalSize =
1878+
SVEStackSize + StackOffset::getFixed((int64_t)MFI.getStackSize());
1879+
unsigned CFIIndex = MF.addFrameInst(createDefCFA(
1880+
*RegInfo, /*FrameReg=*/AArch64::SP, /*Reg=*/AArch64::SP, TotalSize,
1881+
/*LastAdjustmentWasScalable=*/false));
1882+
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
1883+
.addCFIIndex(CFIIndex)
1884+
.setMIFlags(MachineInstr::FrameSetup);
1885+
}
1886+
emitCalleeSavedGPRLocations(MBB, MBBI);
1887+
emitCalleeSavedSVELocations(MBB, MBBI);
1888+
}
18611889
}
18621890

18631891
static void InsertReturnAddressAuth(MachineFunction &MF, MachineBasicBlock &MBB,
@@ -2229,6 +2257,11 @@ void AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
22292257
}
22302258
}
22312259

2260+
bool AArch64FrameLowering::enableCFIFixup(MachineFunction &MF) const {
2261+
return TargetFrameLowering::enableCFIFixup(MF) &&
2262+
MF.getInfo<AArch64FunctionInfo>()->needsAsyncDwarfUnwindInfo(MF);
2263+
}
2264+
22322265
/// getFrameIndexReference - Provide a base+offset reference to an FI slot for
22332266
/// debug info. It's the same as what we use for resolving the code-gen
22342267
/// references for now. FIXME: This can go wrong when references are

‎llvm/lib/Target/AArch64/AArch64FrameLowering.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,8 @@ class AArch64FrameLowering : public TargetFrameLowering {
3535
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
3636
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
3737

38+
bool enableCFIFixup(MachineFunction &MF) const override;
39+
3840
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override;
3941

4042
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI,

‎llvm/test/CodeGen/AArch64/GlobalISel/call-translator-variadic-musttail.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -31,13 +31,13 @@ define i32 @test_musttail_variadic_spill(i32 %arg0, ...) {
3131
; CHECK-LABEL: test_musttail_variadic_spill:
3232
; CHECK: ; %bb.0:
3333
; CHECK-NEXT: sub sp, sp, #224
34-
; CHECK-NEXT: .cfi_def_cfa_offset 224
3534
; CHECK-NEXT: stp x28, x27, [sp, #128] ; 16-byte Folded Spill
3635
; CHECK-NEXT: stp x26, x25, [sp, #144] ; 16-byte Folded Spill
3736
; CHECK-NEXT: stp x24, x23, [sp, #160] ; 16-byte Folded Spill
3837
; CHECK-NEXT: stp x22, x21, [sp, #176] ; 16-byte Folded Spill
3938
; CHECK-NEXT: stp x20, x19, [sp, #192] ; 16-byte Folded Spill
4039
; CHECK-NEXT: stp x29, x30, [sp, #208] ; 16-byte Folded Spill
40+
; CHECK-NEXT: .cfi_def_cfa_offset 224
4141
; CHECK-NEXT: .cfi_offset w30, -8
4242
; CHECK-NEXT: .cfi_offset w29, -16
4343
; CHECK-NEXT: .cfi_offset w19, -24
@@ -103,13 +103,13 @@ define void @f_thunk(ptr %this, ...) {
103103
; CHECK-LABEL: f_thunk:
104104
; CHECK: ; %bb.0:
105105
; CHECK-NEXT: sub sp, sp, #256
106-
; CHECK-NEXT: .cfi_def_cfa_offset 256
107106
; CHECK-NEXT: stp x28, x27, [sp, #160] ; 16-byte Folded Spill
108107
; CHECK-NEXT: stp x26, x25, [sp, #176] ; 16-byte Folded Spill
109108
; CHECK-NEXT: stp x24, x23, [sp, #192] ; 16-byte Folded Spill
110109
; CHECK-NEXT: stp x22, x21, [sp, #208] ; 16-byte Folded Spill
111110
; CHECK-NEXT: stp x20, x19, [sp, #224] ; 16-byte Folded Spill
112111
; CHECK-NEXT: stp x29, x30, [sp, #240] ; 16-byte Folded Spill
112+
; CHECK-NEXT: .cfi_def_cfa_offset 256
113113
; CHECK-NEXT: .cfi_offset w30, -8
114114
; CHECK-NEXT: .cfi_offset w29, -16
115115
; CHECK-NEXT: .cfi_offset w19, -24

‎llvm/test/CodeGen/AArch64/GlobalISel/merge-stores-truncating.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -348,8 +348,8 @@ define dso_local void @trunc_from_larger_src_val(i64 %hold.4.lcssa, ptr %check17
348348
; CHECK-LABEL: trunc_from_larger_src_val:
349349
; CHECK: ; %bb.0:
350350
; CHECK-NEXT: sub sp, sp, #32
351-
; CHECK-NEXT: .cfi_def_cfa_offset 32
352351
; CHECK-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
352+
; CHECK-NEXT: .cfi_def_cfa_offset 32
353353
; CHECK-NEXT: .cfi_offset w30, -8
354354
; CHECK-NEXT: .cfi_offset w29, -16
355355
; CHECK-NEXT: str w0, [sp, #12]

‎llvm/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll

Lines changed: 24 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -99,9 +99,9 @@ entry:
9999
; CHECK: .cfi_startproc
100100
; Check that used callee-saved registers are saved
101101
; CHECK: sub sp, sp, #32
102-
; CHECK: .cfi_def_cfa_offset 32
103102
; CHECK: stp x30, x19, [sp, #16]
104103
; Check correctness of cfi pseudo-instructions
104+
; CHECK: .cfi_def_cfa_offset 32
105105
; CHECK: .cfi_offset w19, -8
106106
; CHECK: .cfi_offset w30, -16
107107
; Check correct access to arguments passed on the stack, through stack pointer
@@ -118,7 +118,6 @@ entry:
118118
; CHECK-MACHO: .cfi_startproc
119119
; Check that used callee-saved registers are saved
120120
; CHECK-MACHO: sub sp, sp, #48
121-
; CHECK-MACHO:.cfi_def_cfa_offset 48
122121
; CHECK-MACHO: stp x20, x19, [sp, #16]
123122
; Check that the frame pointer is created:
124123
; CHECK-MACHO: stp x29, x30, [sp, #32]
@@ -182,18 +181,17 @@ entry:
182181
; CHECK: .cfi_startproc
183182
; Check that used callee-saved registers are saved
184183
; CHECK: stp x29, x30, [sp, #-32]!
185-
; CHECK: .cfi_def_cfa_offset 32
186184
; Check that the frame pointer is created:
187185
; CHECK: str x19, [sp, #16]
188186
; CHECK: mov x29, sp
187+
; Check the dynamic realignment of the stack pointer to a 128-byte boundary
188+
; CHECK: sub x9, sp, #96
189+
; CHECK: and sp, x9, #0xffffffffffffff80
189190
; Check correctness of cfi pseudo-instructions
190191
; CHECK: .cfi_def_cfa w29, 32
191192
; CHECK: .cfi_offset w19, -16
192193
; CHECK: .cfi_offset w30, -24
193194
; CHECK: .cfi_offset w29, -32
194-
; Check the dynamic realignment of the stack pointer to a 128-byte boundary
195-
; CHECK: sub x9, sp, #96
196-
; CHECK: and sp, x9, #0xffffffffffffff80
197195
; Check correct access to arguments passed on the stack, through frame pointer
198196
; CHECK: ldr d[[DARG:[0-9]+]], [x29, #56]
199197
; CHECK: ldr w[[IARG:[0-9]+]], [x29, #40]
@@ -211,19 +209,18 @@ entry:
211209
; CHECK-MACHO: .cfi_startproc
212210
; Check that used callee-saved registers are saved
213211
; CHECK-MACHO: stp x20, x19, [sp, #-32]!
214-
; CHECK-MACHO: .cfi_def_cfa_offset 32
215212
; Check that the frame pointer is created:
216213
; CHECK-MACHO: stp x29, x30, [sp, #16]
217214
; CHECK-MACHO: add x29, sp, #16
215+
; Check the dynamic realignment of the stack pointer to a 128-byte boundary
216+
; CHECK-MACHO: sub x9, sp, #96
217+
; CHECK-MACHO: and sp, x9, #0xffffffffffffff80
218218
; Check correctness of cfi pseudo-instructions
219219
; CHECK-MACHO: .cfi_def_cfa w29, 16
220220
; CHECK-MACHO: .cfi_offset w30, -8
221221
; CHECK-MACHO: .cfi_offset w29, -16
222222
; CHECK-MACHO: .cfi_offset w19, -24
223223
; CHECK-MACHO: .cfi_offset w20, -32
224-
; Check the dynamic realignment of the stack pointer to a 128-byte boundary
225-
; CHECK-MACHO: sub x9, sp, #96
226-
; CHECK-MACHO: and sp, x9, #0xffffffffffffff80
227224
; Check correct access to arguments passed on the stack, through frame pointer
228225
; CHECK-MACHO: ldr d[[DARG:[0-9]+]], [x29, #32]
229226
; CHECK-MACHO: ldr w[[IARG:[0-9]+]], [x29, #20]
@@ -288,19 +285,18 @@ entry:
288285
; CHECK: .cfi_startproc
289286
; Check that used callee-saved registers are saved
290287
; CHECK: stp x29, x30, [sp, #-32]!
291-
; CHECK: .cfi_def_cfa_offset 32
292288
; Check that the frame pointer is created:
293289
; CHECK: stp x20, x19, [sp, #16]
294290
; CHECK: mov x29, sp
291+
; Check that space is reserved on the stack for the local variable,
292+
; rounded up to a multiple of 16 to keep the stack pointer 16-byte aligned.
293+
; CHECK: sub sp, sp, #16
295294
; Check correctness of cfi pseudo-instructions
296295
; CHECK: .cfi_def_cfa w29, 32
297296
; CHECK: .cfi_offset w19, -8
298297
; CHECK: .cfi_offset w20, -16
299298
; CHECK: .cfi_offset w30, -24
300299
; CHECK: .cfi_offset w29, -32
301-
; Check that space is reserved on the stack for the local variable,
302-
; rounded up to a multiple of 16 to keep the stack pointer 16-byte aligned.
303-
; CHECK: sub sp, sp, #16
304300
; Check correct access to arguments passed on the stack, through frame pointer
305301
; CHECK: ldr w[[IARG:[0-9]+]], [x29, #40]
306302
; Check correct reservation of 16-byte aligned VLA (size in w0) on stack
@@ -388,25 +384,24 @@ entry:
388384
; CHECK: .cfi_startproc
389385
; Check that used callee-saved registers are saved
390386
; CHECK: stp x29, x30, [sp, #-48]!
391-
; CHECK: .cfi_def_cfa_offset 48
392387
; CHECK: str x21, [sp, #16]
393388
; CHECK: stp x20, x19, [sp, #32]
394389
; Check that the frame pointer is created:
395390
; CHECK: mov x29, sp
396-
; Check correctness of cfi pseudo-instructions
397-
; CHECK: .cfi_def_cfa w29, 48
398-
; CHECK: .cfi_offset w19, -8
399-
; CHECK: .cfi_offset w20, -16
400-
; CHECK: .cfi_offset w21, -32
401-
; CHECK: .cfi_offset w30, -40
402-
; CHECK: .cfi_offset w29, -48
403391
; Check that the stack pointer gets re-aligned to 128
404392
; bytes & the base pointer (x19) gets initialized to
405393
; this 128-byte aligned area for local variables &
406394
; spill slots
407395
; CHECK: sub x9, sp, #80
408396
; CHECK: and sp, x9, #0xffffffffffffff80
409397
; CHECK: mov x19, sp
398+
; Check correctness of cfi pseudo-instructions
399+
; CHECK: .cfi_def_cfa w29, 48
400+
; CHECK: .cfi_offset w19, -8
401+
; CHECK: .cfi_offset w20, -16
402+
; CHECK: .cfi_offset w21, -32
403+
; CHECK: .cfi_offset w30, -40
404+
; CHECK: .cfi_offset w29, -48
410405
; Check correct access to arguments passed on the stack, through frame pointer
411406
; CHECK: ldr w[[IARG:[0-9]+]], [x29, #56]
412407
; Check correct reservation of 16-byte aligned VLA (size in w0) on stack
@@ -434,11 +429,17 @@ entry:
434429
; CHECK-MACHO: .cfi_startproc
435430
; Check that used callee-saved registers are saved
436431
; CHECK-MACHO: stp x22, x21, [sp, #-48]!
437-
; CHECK-MACHO: .cfi_def_cfa_offset 48
438432
; CHECK-MACHO: stp x20, x19, [sp, #16]
439433
; Check that the frame pointer is created:
440434
; CHECK-MACHO: stp x29, x30, [sp, #32]
441435
; CHECK-MACHO: add x29, sp, #32
436+
; Check that the stack pointer gets re-aligned to 128
437+
; bytes & the base pointer (x19) gets initialized to
438+
; this 128-byte aligned area for local variables &
439+
; spill slots
440+
; CHECK-MACHO: sub x9, sp, #80
441+
; CHECK-MACHO: and sp, x9, #0xffffffffffffff80
442+
; CHECK-MACHO: mov x19, sp
442443
; Check correctness of cfi pseudo-instructions
443444
; CHECK-MACHO: .cfi_def_cfa w29, 16
444445
; CHECK-MACHO: .cfi_offset w30, -8
@@ -447,13 +448,6 @@ entry:
447448
; CHECK-MACHO: .cfi_offset w20, -32
448449
; CHECK-MACHO: .cfi_offset w21, -40
449450
; CHECK-MACHO: .cfi_offset w22, -48
450-
; Check that the stack pointer gets re-aligned to 128
451-
; bytes & the base pointer (x19) gets initialized to
452-
; this 128-byte aligned area for local variables &
453-
; spill slots
454-
; CHECK-MACHO: sub x9, sp, #80
455-
; CHECK-MACHO: and sp, x9, #0xffffffffffffff80
456-
; CHECK-MACHO: mov x19, sp
457451
; Check correct access to arguments passed on the stack, through frame pointer
458452
; CHECK-MACHO: ldr w[[IARG:[0-9]+]], [x29, #20]
459453
; Check correct reservation of 16-byte aligned VLA (size in w0) on stack

‎llvm/test/CodeGen/AArch64/aarch64-fastcc-stackup.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,8 +21,8 @@ define fastcc i64 @baz() {
2121
; CHECK-LABEL: baz:
2222
; CHECK: // %bb.0: // %entry
2323
; CHECK-NEXT: sub sp, sp, #32
24-
; CHECK-NEXT: .cfi_def_cfa_offset 32
2524
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
25+
; CHECK-NEXT: .cfi_def_cfa_offset 32
2626
; CHECK-NEXT: .cfi_offset w30, -16
2727
; CHECK-NEXT: mov x8, sp
2828
; CHECK-NEXT: mov x7, xzr

‎llvm/test/CodeGen/AArch64/aarch64-mops-consecutive.ll

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -10,11 +10,10 @@ define void @consecutive() {
1010
; CHECK-MOPS-LABEL: consecutive:
1111
; CHECK-MOPS: // %bb.0: // %entry
1212
; CHECK-MOPS-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
13-
; CHECK-MOPS-NEXT: .cfi_def_cfa_offset 16
14-
; CHECK-MOPS-NEXT: .cfi_offset w30, -8
15-
; CHECK-MOPS-NEXT: .cfi_offset w29, -16
1613
; CHECK-MOPS-NEXT: sub sp, sp, #2016
1714
; CHECK-MOPS-NEXT: .cfi_def_cfa_offset 2032
15+
; CHECK-MOPS-NEXT: .cfi_offset w30, -8
16+
; CHECK-MOPS-NEXT: .cfi_offset w29, -16
1817
; CHECK-MOPS-NEXT: mov w8, #1000
1918
; CHECK-MOPS-NEXT: add x9, sp, #8
2019
; CHECK-MOPS-NEXT: adrp x10, .LCPI0_0

‎llvm/test/CodeGen/AArch64/aarch64-mops.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -690,8 +690,8 @@ define void @memset_size(ptr %dst, i64 %size, i32 %value) {
690690
; GISel-WITHOUT-MOPS-O0-LABEL: memset_size:
691691
; GISel-WITHOUT-MOPS-O0: // %bb.0: // %entry
692692
; GISel-WITHOUT-MOPS-O0-NEXT: sub sp, sp, #32
693-
; GISel-WITHOUT-MOPS-O0-NEXT: .cfi_def_cfa_offset 32
694693
; GISel-WITHOUT-MOPS-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
694+
; GISel-WITHOUT-MOPS-O0-NEXT: .cfi_def_cfa_offset 32
695695
; GISel-WITHOUT-MOPS-O0-NEXT: .cfi_offset w30, -16
696696
; GISel-WITHOUT-MOPS-O0-NEXT: str x1, [sp, #8] // 8-byte Folded Spill
697697
; GISel-WITHOUT-MOPS-O0-NEXT: mov w1, w2
@@ -759,8 +759,8 @@ define void @memset_size_volatile(ptr %dst, i64 %size, i32 %value) {
759759
; GISel-WITHOUT-MOPS-O0-LABEL: memset_size_volatile:
760760
; GISel-WITHOUT-MOPS-O0: // %bb.0: // %entry
761761
; GISel-WITHOUT-MOPS-O0-NEXT: sub sp, sp, #32
762-
; GISel-WITHOUT-MOPS-O0-NEXT: .cfi_def_cfa_offset 32
763762
; GISel-WITHOUT-MOPS-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
763+
; GISel-WITHOUT-MOPS-O0-NEXT: .cfi_def_cfa_offset 32
764764
; GISel-WITHOUT-MOPS-O0-NEXT: .cfi_offset w30, -16
765765
; GISel-WITHOUT-MOPS-O0-NEXT: str x1, [sp, #8] // 8-byte Folded Spill
766766
; GISel-WITHOUT-MOPS-O0-NEXT: mov w1, w2

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