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[TableGen][SchedModels] Fix aliasing of SchedWriteVariant
Differential revision: https://reviews.llvm.org/D89114
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4 files changed

+146
-75
lines changed

4 files changed

+146
-75
lines changed

‎llvm/test/TableGen/sched-aliases.td

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,48 @@
1+
// REQUIRES: asserts
2+
// REQUIRES: aarch64-registered-target
3+
// RUN: llvm-tblgen -gen-instr-info %s -I%p/../../include -I%p/../../lib/Target/AArch64 -o %t -debug-only=subtarget-emitter 2>&1 | FileCheck %s
4+
5+
// Check that we've defined scheduling classes for FMOVv2f32_ns and FMOVv2f64 for Model0
6+
// CHECK: InstRW: New SC [[SC:[0-9]+]]:FMOVv2f32_ns on Model0
7+
// CHECK: InstRW: New SC [[SC2:[0-9]+]]:FMOVv2f64_ns on Model0
8+
9+
// Generic transition for WriteV should be defined for Model0 as well as for
10+
// all instructions without explicitly defined scheduling classes.
11+
// CHECK: Adding transition from WriteV({{[0-9]+}}) to Model0WriteV_4cyc({{[0-9]+}}) on processor indices
12+
// CHECK: Adding transition from WriteV({{[0-9]+}}) to Model0WriteV_2cyc({{[0-9]+}}) on processor indices
13+
14+
// Transition from FMOVv2f64_ns should still be added for Model0,
15+
// even though we've defined custom scheduling class.
16+
// CHECK: Adding transition from FMOVv2f64_ns([[SC2]]) to Model0WriteV_4cyc({{[0-9]+}}) on processor indices
17+
// CHECK-NEXT: Adding transition from FMOVv2f64_ns([[SC2]]) to Model0WriteV_2cyc({{[0-9]+}}) on processor indices
18+
19+
// Transition from FMOVv2f32_ns should not be added for Model0,
20+
// because custom sched class for it is defined and it's not variant.
21+
// CHECK-NOT: Adding transition from FMOVv2f32_ns([[SC]])
22+
23+
include "AArch64.td"
24+
25+
def Model0 : SchedMachineModel {
26+
let CompleteModel = 0;
27+
}
28+
29+
def Model0UnitV : ProcResource<1> { let BufferSize = 0; }
30+
31+
let SchedModel = Model0 in {
32+
33+
def Model0WriteV_4cyc : SchedWriteRes<[Model0UnitV]> { let Latency = 4; }
34+
def Model0WriteV_2cyc : SchedWriteRes<[Model0UnitV]> { let Latency = 2; }
35+
def Model0WriteV_1cyc : SchedWriteRes<[Model0UnitV]> { let Latency = 1; }
36+
37+
def Model0QFormPred : MCSchedPredicate<CheckQForm>;
38+
def Model0WriteV : SchedWriteVariant<[
39+
SchedVar<Model0QFormPred, [Model0WriteV_4cyc]>,
40+
SchedVar<NoSchedPred, [Model0WriteV_2cyc]>]>;
41+
42+
def : SchedAlias<WriteV, Model0WriteV>;
43+
44+
def : InstRW<[Model0WriteV_1cyc], (instrs FMOVv2f32_ns)>;
45+
def : InstRW<[WriteV], (instrs FMOVv2f64_ns)>;
46+
}
47+
48+
def : ProcessorModel<"foo-0-model", Model0, []>;

‎llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s

Lines changed: 61 additions & 61 deletions
Original file line numberDiff line numberDiff line change
@@ -1561,31 +1561,31 @@
15611561
# CHECK-NEXT: 1 2 1.00 sxtablt r6, r2, r9, ror #8
15621562
# CHECK-NEXT: 1 2 1.00 sxtab r5, r1, r4, ror #16
15631563
# CHECK-NEXT: 1 2 1.00 sxtab r7, r8, r3, ror #24
1564-
# CHECK-NEXT: 1 2 1.00 sxtab16ge r0, r1, r4
1565-
# CHECK-NEXT: 1 2 1.00 sxtab16 r6, r2, r7
1566-
# CHECK-NEXT: 1 2 1.00 sxtab16 r3, r5, r8, ror #8
1567-
# CHECK-NEXT: 1 2 1.00 sxtab16 r3, r2, r1, ror #16
1568-
# CHECK-NEXT: 1 2 1.00 sxtab16eq r1, r2, r3, ror #24
1564+
# CHECK-NEXT: 1 4 1.00 sxtab16ge r0, r1, r4
1565+
# CHECK-NEXT: 1 4 1.00 sxtab16 r6, r2, r7
1566+
# CHECK-NEXT: 1 4 1.00 sxtab16 r3, r5, r8, ror #8
1567+
# CHECK-NEXT: 1 4 1.00 sxtab16 r3, r2, r1, ror #16
1568+
# CHECK-NEXT: 1 4 1.00 sxtab16eq r1, r2, r3, ror #24
15691569
# CHECK-NEXT: 1 2 1.00 sxtah r1, r3, r9
15701570
# CHECK-NEXT: 1 2 1.00 sxtahhi r6, r1, r6
15711571
# CHECK-NEXT: 1 2 1.00 sxtah r3, r8, r3, ror #8
15721572
# CHECK-NEXT: 1 2 1.00 sxtahlo r2, r2, r4, ror #16
15731573
# CHECK-NEXT: 1 2 1.00 sxtah r9, r3, r3, ror #24
1574-
# CHECK-NEXT: 1 2 1.00 sxtbge r2, r4
1575-
# CHECK-NEXT: 1 2 1.00 sxtb r5, r6
1576-
# CHECK-NEXT: 1 2 1.00 sxtb r6, r9, ror #8
1577-
# CHECK-NEXT: 1 2 1.00 sxtblo r5, r1, ror #16
1578-
# CHECK-NEXT: 1 2 1.00 sxtb r8, r3, ror #24
1574+
# CHECK-NEXT: 1 1 0.50 sxtbge r2, r4
1575+
# CHECK-NEXT: 1 1 0.50 sxtb r5, r6
1576+
# CHECK-NEXT: 1 1 0.50 sxtb r6, r9, ror #8
1577+
# CHECK-NEXT: 1 1 0.50 sxtblo r5, r1, ror #16
1578+
# CHECK-NEXT: 1 1 0.50 sxtb r8, r3, ror #24
15791579
# CHECK-NEXT: 1 2 1.00 sxtb16 r1, r4
15801580
# CHECK-NEXT: 1 2 1.00 sxtb16 r6, r7
15811581
# CHECK-NEXT: 1 2 1.00 sxtb16hs r3, r5, ror #8
15821582
# CHECK-NEXT: 1 2 1.00 sxtb16 r3, r1, ror #16
15831583
# CHECK-NEXT: 1 2 1.00 sxtb16ge r2, r3, ror #24
1584-
# CHECK-NEXT: 1 2 1.00 sxthne r3, r9
1585-
# CHECK-NEXT: 1 2 1.00 sxth r1, r6
1586-
# CHECK-NEXT: 1 2 1.00 sxth r3, r8, ror #8
1587-
# CHECK-NEXT: 1 2 1.00 sxthle r2, r2, ror #16
1588-
# CHECK-NEXT: 1 2 1.00 sxth r9, r3, ror #24
1584+
# CHECK-NEXT: 1 1 0.50 sxthne r3, r9
1585+
# CHECK-NEXT: 1 1 0.50 sxth r1, r6
1586+
# CHECK-NEXT: 1 1 0.50 sxth r3, r8, ror #8
1587+
# CHECK-NEXT: 1 1 0.50 sxthle r2, r2, ror #16
1588+
# CHECK-NEXT: 1 1 0.50 sxth r9, r3, ror #24
15891589
# CHECK-NEXT: 1 1 0.50 teq r5, #61440
15901590
# CHECK-NEXT: 1 1 0.50 teq r7, #-2147483638
15911591
# CHECK-NEXT: 1 1 0.50 teq r7, #40, #2
@@ -1674,31 +1674,31 @@
16741674
# CHECK-NEXT: 1 2 1.00 uxtablt r6, r2, r9, ror #8
16751675
# CHECK-NEXT: 1 2 1.00 uxtab r5, r1, r4, ror #16
16761676
# CHECK-NEXT: 1 2 1.00 uxtab r7, r8, r3, ror #24
1677-
# CHECK-NEXT: 1 2 1.00 uxtab16ge r0, r1, r4
1678-
# CHECK-NEXT: 1 2 1.00 uxtab16 r6, r2, r7
1679-
# CHECK-NEXT: 1 2 1.00 uxtab16 r3, r5, r8, ror #8
1680-
# CHECK-NEXT: 1 2 1.00 uxtab16 r3, r2, r1, ror #16
1681-
# CHECK-NEXT: 1 2 1.00 uxtab16eq r1, r2, r3, ror #24
1677+
# CHECK-NEXT: 1 4 1.00 uxtab16ge r0, r1, r4
1678+
# CHECK-NEXT: 1 4 1.00 uxtab16 r6, r2, r7
1679+
# CHECK-NEXT: 1 4 1.00 uxtab16 r3, r5, r8, ror #8
1680+
# CHECK-NEXT: 1 4 1.00 uxtab16 r3, r2, r1, ror #16
1681+
# CHECK-NEXT: 1 4 1.00 uxtab16eq r1, r2, r3, ror #24
16821682
# CHECK-NEXT: 1 2 1.00 uxtah r1, r3, r9
16831683
# CHECK-NEXT: 1 2 1.00 uxtahhi r6, r1, r6
16841684
# CHECK-NEXT: 1 2 1.00 uxtah r3, r8, r3, ror #8
16851685
# CHECK-NEXT: 1 2 1.00 uxtahlo r2, r2, r4, ror #16
16861686
# CHECK-NEXT: 1 2 1.00 uxtah r9, r3, r3, ror #24
1687-
# CHECK-NEXT: 1 2 1.00 uxtbge r2, r4
1688-
# CHECK-NEXT: 1 2 1.00 uxtb r5, r6
1689-
# CHECK-NEXT: 1 2 1.00 uxtb r6, r9, ror #8
1690-
# CHECK-NEXT: 1 2 1.00 uxtblo r5, r1, ror #16
1691-
# CHECK-NEXT: 1 2 1.00 uxtb r8, r3, ror #24
1687+
# CHECK-NEXT: 1 1 0.50 uxtbge r2, r4
1688+
# CHECK-NEXT: 1 1 0.50 uxtb r5, r6
1689+
# CHECK-NEXT: 1 1 0.50 uxtb r6, r9, ror #8
1690+
# CHECK-NEXT: 1 1 0.50 uxtblo r5, r1, ror #16
1691+
# CHECK-NEXT: 1 1 0.50 uxtb r8, r3, ror #24
16921692
# CHECK-NEXT: 1 2 1.00 uxtb16 r1, r4
16931693
# CHECK-NEXT: 1 2 1.00 uxtb16 r6, r7
16941694
# CHECK-NEXT: 1 2 1.00 uxtb16hs r3, r5, ror #8
16951695
# CHECK-NEXT: 1 2 1.00 uxtb16 r3, r1, ror #16
16961696
# CHECK-NEXT: 1 2 1.00 uxtb16ge r2, r3, ror #24
1697-
# CHECK-NEXT: 1 2 1.00 uxthne r3, r9
1698-
# CHECK-NEXT: 1 2 1.00 uxth r1, r6
1699-
# CHECK-NEXT: 1 2 1.00 uxth r3, r8, ror #8
1700-
# CHECK-NEXT: 1 2 1.00 uxthle r2, r2, ror #16
1701-
# CHECK-NEXT: 1 2 1.00 uxth r9, r3, ror #24
1697+
# CHECK-NEXT: 1 1 0.50 uxthne r3, r9
1698+
# CHECK-NEXT: 1 1 0.50 uxth r1, r6
1699+
# CHECK-NEXT: 1 1 0.50 uxth r3, r8, ror #8
1700+
# CHECK-NEXT: 1 1 0.50 uxthle r2, r2, ror #16
1701+
# CHECK-NEXT: 1 1 0.50 uxth r9, r3, ror #24
17021702
# CHECK-NEXT: 0 0 0.00 * * U wfe
17031703
# CHECK-NEXT: 0 0 0.00 * * U wfehi
17041704
# CHECK-NEXT: 0 0 0.00 * * U wfi
@@ -1719,7 +1719,7 @@
17191719

17201720
# CHECK: Resource pressure per iteration:
17211721
# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6]
1722-
# CHECK-NEXT: 8.00 148.50 148.50 161.00 527.00 12.00 - -
1722+
# CHECK-NEXT: 8.00 158.50 158.50 171.00 497.00 12.00 - -
17231723

17241724
# CHECK: Resource pressure by instruction:
17251725
# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] Instructions:
@@ -2425,31 +2425,31 @@
24252425
# CHECK-NEXT: - - - - 1.00 - - - sxtablt r6, r2, r9, ror #8
24262426
# CHECK-NEXT: - - - - 1.00 - - - sxtab r5, r1, r4, ror #16
24272427
# CHECK-NEXT: - - - - 1.00 - - - sxtab r7, r8, r3, ror #24
2428-
# CHECK-NEXT: - - - - 1.00 - - - sxtab16ge r0, r1, r4
2429-
# CHECK-NEXT: - - - - 1.00 - - - sxtab16 r6, r2, r7
2430-
# CHECK-NEXT: - - - - 1.00 - - - sxtab16 r3, r5, r8, ror #8
2431-
# CHECK-NEXT: - - - - 1.00 - - - sxtab16 r3, r2, r1, ror #16
2432-
# CHECK-NEXT: - - - - 1.00 - - - sxtab16eq r1, r2, r3, ror #24
2428+
# CHECK-NEXT: - - - 1.00 - - - - sxtab16ge r0, r1, r4
2429+
# CHECK-NEXT: - - - 1.00 - - - - sxtab16 r6, r2, r7
2430+
# CHECK-NEXT: - - - 1.00 - - - - sxtab16 r3, r5, r8, ror #8
2431+
# CHECK-NEXT: - - - 1.00 - - - - sxtab16 r3, r2, r1, ror #16
2432+
# CHECK-NEXT: - - - 1.00 - - - - sxtab16eq r1, r2, r3, ror #24
24332433
# CHECK-NEXT: - - - - 1.00 - - - sxtah r1, r3, r9
24342434
# CHECK-NEXT: - - - - 1.00 - - - sxtahhi r6, r1, r6
24352435
# CHECK-NEXT: - - - - 1.00 - - - sxtah r3, r8, r3, ror #8
24362436
# CHECK-NEXT: - - - - 1.00 - - - sxtahlo r2, r2, r4, ror #16
24372437
# CHECK-NEXT: - - - - 1.00 - - - sxtah r9, r3, r3, ror #24
2438-
# CHECK-NEXT: - - - - 1.00 - - - sxtbge r2, r4
2439-
# CHECK-NEXT: - - - - 1.00 - - - sxtb r5, r6
2440-
# CHECK-NEXT: - - - - 1.00 - - - sxtb r6, r9, ror #8
2441-
# CHECK-NEXT: - - - - 1.00 - - - sxtblo r5, r1, ror #16
2442-
# CHECK-NEXT: - - - - 1.00 - - - sxtb r8, r3, ror #24
2438+
# CHECK-NEXT: - 0.50 0.50 - - - - - sxtbge r2, r4
2439+
# CHECK-NEXT: - 0.50 0.50 - - - - - sxtb r5, r6
2440+
# CHECK-NEXT: - 0.50 0.50 - - - - - sxtb r6, r9, ror #8
2441+
# CHECK-NEXT: - 0.50 0.50 - - - - - sxtblo r5, r1, ror #16
2442+
# CHECK-NEXT: - 0.50 0.50 - - - - - sxtb r8, r3, ror #24
24432443
# CHECK-NEXT: - - - - 1.00 - - - sxtb16 r1, r4
24442444
# CHECK-NEXT: - - - - 1.00 - - - sxtb16 r6, r7
24452445
# CHECK-NEXT: - - - - 1.00 - - - sxtb16hs r3, r5, ror #8
24462446
# CHECK-NEXT: - - - - 1.00 - - - sxtb16 r3, r1, ror #16
24472447
# CHECK-NEXT: - - - - 1.00 - - - sxtb16ge r2, r3, ror #24
2448-
# CHECK-NEXT: - - - - 1.00 - - - sxthne r3, r9
2449-
# CHECK-NEXT: - - - - 1.00 - - - sxth r1, r6
2450-
# CHECK-NEXT: - - - - 1.00 - - - sxth r3, r8, ror #8
2451-
# CHECK-NEXT: - - - - 1.00 - - - sxthle r2, r2, ror #16
2452-
# CHECK-NEXT: - - - - 1.00 - - - sxth r9, r3, ror #24
2448+
# CHECK-NEXT: - 0.50 0.50 - - - - - sxthne r3, r9
2449+
# CHECK-NEXT: - 0.50 0.50 - - - - - sxth r1, r6
2450+
# CHECK-NEXT: - 0.50 0.50 - - - - - sxth r3, r8, ror #8
2451+
# CHECK-NEXT: - 0.50 0.50 - - - - - sxthle r2, r2, ror #16
2452+
# CHECK-NEXT: - 0.50 0.50 - - - - - sxth r9, r3, ror #24
24532453
# CHECK-NEXT: - 0.50 0.50 - - - - - teq r5, #61440
24542454
# CHECK-NEXT: - 0.50 0.50 - - - - - teq r7, #-2147483638
24552455
# CHECK-NEXT: - 0.50 0.50 - - - - - teq r7, #40, #2
@@ -2538,31 +2538,31 @@
25382538
# CHECK-NEXT: - - - - 1.00 - - - uxtablt r6, r2, r9, ror #8
25392539
# CHECK-NEXT: - - - - 1.00 - - - uxtab r5, r1, r4, ror #16
25402540
# CHECK-NEXT: - - - - 1.00 - - - uxtab r7, r8, r3, ror #24
2541-
# CHECK-NEXT: - - - - 1.00 - - - uxtab16ge r0, r1, r4
2542-
# CHECK-NEXT: - - - - 1.00 - - - uxtab16 r6, r2, r7
2543-
# CHECK-NEXT: - - - - 1.00 - - - uxtab16 r3, r5, r8, ror #8
2544-
# CHECK-NEXT: - - - - 1.00 - - - uxtab16 r3, r2, r1, ror #16
2545-
# CHECK-NEXT: - - - - 1.00 - - - uxtab16eq r1, r2, r3, ror #24
2541+
# CHECK-NEXT: - - - 1.00 - - - - uxtab16ge r0, r1, r4
2542+
# CHECK-NEXT: - - - 1.00 - - - - uxtab16 r6, r2, r7
2543+
# CHECK-NEXT: - - - 1.00 - - - - uxtab16 r3, r5, r8, ror #8
2544+
# CHECK-NEXT: - - - 1.00 - - - - uxtab16 r3, r2, r1, ror #16
2545+
# CHECK-NEXT: - - - 1.00 - - - - uxtab16eq r1, r2, r3, ror #24
25462546
# CHECK-NEXT: - - - - 1.00 - - - uxtah r1, r3, r9
25472547
# CHECK-NEXT: - - - - 1.00 - - - uxtahhi r6, r1, r6
25482548
# CHECK-NEXT: - - - - 1.00 - - - uxtah r3, r8, r3, ror #8
25492549
# CHECK-NEXT: - - - - 1.00 - - - uxtahlo r2, r2, r4, ror #16
25502550
# CHECK-NEXT: - - - - 1.00 - - - uxtah r9, r3, r3, ror #24
2551-
# CHECK-NEXT: - - - - 1.00 - - - uxtbge r2, r4
2552-
# CHECK-NEXT: - - - - 1.00 - - - uxtb r5, r6
2553-
# CHECK-NEXT: - - - - 1.00 - - - uxtb r6, r9, ror #8
2554-
# CHECK-NEXT: - - - - 1.00 - - - uxtblo r5, r1, ror #16
2555-
# CHECK-NEXT: - - - - 1.00 - - - uxtb r8, r3, ror #24
2551+
# CHECK-NEXT: - 0.50 0.50 - - - - - uxtbge r2, r4
2552+
# CHECK-NEXT: - 0.50 0.50 - - - - - uxtb r5, r6
2553+
# CHECK-NEXT: - 0.50 0.50 - - - - - uxtb r6, r9, ror #8
2554+
# CHECK-NEXT: - 0.50 0.50 - - - - - uxtblo r5, r1, ror #16
2555+
# CHECK-NEXT: - 0.50 0.50 - - - - - uxtb r8, r3, ror #24
25562556
# CHECK-NEXT: - - - - 1.00 - - - uxtb16 r1, r4
25572557
# CHECK-NEXT: - - - - 1.00 - - - uxtb16 r6, r7
25582558
# CHECK-NEXT: - - - - 1.00 - - - uxtb16hs r3, r5, ror #8
25592559
# CHECK-NEXT: - - - - 1.00 - - - uxtb16 r3, r1, ror #16
25602560
# CHECK-NEXT: - - - - 1.00 - - - uxtb16ge r2, r3, ror #24
2561-
# CHECK-NEXT: - - - - 1.00 - - - uxthne r3, r9
2562-
# CHECK-NEXT: - - - - 1.00 - - - uxth r1, r6
2563-
# CHECK-NEXT: - - - - 1.00 - - - uxth r3, r8, ror #8
2564-
# CHECK-NEXT: - - - - 1.00 - - - uxthle r2, r2, ror #16
2565-
# CHECK-NEXT: - - - - 1.00 - - - uxth r9, r3, ror #24
2561+
# CHECK-NEXT: - 0.50 0.50 - - - - - uxthne r3, r9
2562+
# CHECK-NEXT: - 0.50 0.50 - - - - - uxth r1, r6
2563+
# CHECK-NEXT: - 0.50 0.50 - - - - - uxth r3, r8, ror #8
2564+
# CHECK-NEXT: - 0.50 0.50 - - - - - uxthle r2, r2, ror #16
2565+
# CHECK-NEXT: - 0.50 0.50 - - - - - uxth r9, r3, ror #24
25662566
# CHECK-NEXT: - - - - - - - - wfe
25672567
# CHECK-NEXT: - - - - - - - - wfehi
25682568
# CHECK-NEXT: - - - - - - - - wfi

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