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[AMDGPU] Min/max changes for GFX12 (#75214)
Co-authored-by: Stanislav Mekhanoshin <[email protected]>
1 parent c9e1003 commit 6eec801

30 files changed

+4922
-17
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,8 @@ static bool fnegFoldsIntoMI(const MachineInstr &MI) {
2929
case AMDGPU::G_FMAXNUM:
3030
case AMDGPU::G_FMINNUM_IEEE:
3131
case AMDGPU::G_FMAXNUM_IEEE:
32+
case AMDGPU::G_FMINIMUM:
33+
case AMDGPU::G_FMAXIMUM:
3234
case AMDGPU::G_FSIN:
3335
case AMDGPU::G_FPEXT:
3436
case AMDGPU::G_INTRINSIC_TRUNC:
@@ -174,6 +176,10 @@ static unsigned inverseMinMax(unsigned Opc) {
174176
return AMDGPU::G_FMINNUM_IEEE;
175177
case AMDGPU::G_FMINNUM_IEEE:
176178
return AMDGPU::G_FMAXNUM_IEEE;
179+
case AMDGPU::G_FMAXIMUM:
180+
return AMDGPU::G_FMINIMUM;
181+
case AMDGPU::G_FMINIMUM:
182+
return AMDGPU::G_FMAXIMUM;
177183
case AMDGPU::G_AMDGPU_FMAX_LEGACY:
178184
return AMDGPU::G_AMDGPU_FMIN_LEGACY;
179185
case AMDGPU::G_AMDGPU_FMIN_LEGACY:
@@ -207,6 +213,8 @@ bool AMDGPUCombinerHelper::matchFoldableFneg(MachineInstr &MI,
207213
case AMDGPU::G_FMAXNUM:
208214
case AMDGPU::G_FMINNUM_IEEE:
209215
case AMDGPU::G_FMAXNUM_IEEE:
216+
case AMDGPU::G_FMINIMUM:
217+
case AMDGPU::G_FMAXIMUM:
210218
case AMDGPU::G_AMDGPU_FMIN_LEGACY:
211219
case AMDGPU::G_AMDGPU_FMAX_LEGACY:
212220
// 0 doesn't have a negated inline immediate.
@@ -304,6 +312,8 @@ void AMDGPUCombinerHelper::applyFoldableFneg(MachineInstr &MI,
304312
case AMDGPU::G_FMAXNUM:
305313
case AMDGPU::G_FMINNUM_IEEE:
306314
case AMDGPU::G_FMAXNUM_IEEE:
315+
case AMDGPU::G_FMINIMUM:
316+
case AMDGPU::G_FMAXIMUM:
307317
case AMDGPU::G_AMDGPU_FMIN_LEGACY:
308318
case AMDGPU::G_AMDGPU_FMAX_LEGACY: {
309319
NegateOperand(MatchInfo->getOperand(1));

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -585,6 +585,8 @@ static bool fnegFoldsIntoOpcode(unsigned Opc) {
585585
case ISD::FMAXNUM:
586586
case ISD::FMINNUM_IEEE:
587587
case ISD::FMAXNUM_IEEE:
588+
case ISD::FMINIMUM:
589+
case ISD::FMAXIMUM:
588590
case ISD::SELECT:
589591
case ISD::FSIN:
590592
case ISD::FTRUNC:
@@ -4572,6 +4574,10 @@ static unsigned inverseMinMax(unsigned Opc) {
45724574
return ISD::FMINNUM_IEEE;
45734575
case ISD::FMINNUM_IEEE:
45744576
return ISD::FMAXNUM_IEEE;
4577+
case ISD::FMAXIMUM:
4578+
return ISD::FMINIMUM;
4579+
case ISD::FMINIMUM:
4580+
return ISD::FMAXIMUM;
45754581
case AMDGPUISD::FMAX_LEGACY:
45764582
return AMDGPUISD::FMIN_LEGACY;
45774583
case AMDGPUISD::FMIN_LEGACY:
@@ -4695,6 +4701,8 @@ SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N,
46954701
case ISD::FMINNUM:
46964702
case ISD::FMAXNUM_IEEE:
46974703
case ISD::FMINNUM_IEEE:
4704+
case ISD::FMINIMUM:
4705+
case ISD::FMAXIMUM:
46984706
case AMDGPUISD::FMAX_LEGACY:
46994707
case AMDGPUISD::FMIN_LEGACY: {
47004708
// fneg (fmaxnum x, y) -> fminnum (fneg x), (fneg y)
@@ -5305,6 +5313,8 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
53055313
NODE_NAME_CASE(FMED3)
53065314
NODE_NAME_CASE(SMED3)
53075315
NODE_NAME_CASE(UMED3)
5316+
NODE_NAME_CASE(FMAXIMUM3)
5317+
NODE_NAME_CASE(FMINIMUM3)
53085318
NODE_NAME_CASE(FDOT2)
53095319
NODE_NAME_CASE(URECIP)
53105320
NODE_NAME_CASE(DIV_SCALE)
@@ -5759,6 +5769,8 @@ bool AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,
57595769
case AMDGPUISD::FMED3:
57605770
case AMDGPUISD::FMIN3:
57615771
case AMDGPUISD::FMAX3:
5772+
case AMDGPUISD::FMINIMUM3:
5773+
case AMDGPUISD::FMAXIMUM3:
57625774
case AMDGPUISD::FMAD_FTZ: {
57635775
if (SNaN)
57645776
return true;

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -449,6 +449,8 @@ enum NodeType : unsigned {
449449
FMED3,
450450
SMED3,
451451
UMED3,
452+
FMAXIMUM3,
453+
FMINIMUM3,
452454
FDOT2,
453455
URECIP,
454456
DIV_SCALE,

‎llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -170,6 +170,11 @@ def AMDGPUfmax3 : SDNode<"AMDGPUISD::FMAX3", SDTFPTernaryOp,
170170
[/*SDNPCommutative, SDNPAssociative*/]
171171
>;
172172

173+
// out = max(a, b, c) a, b and c are floats. Operation is IEEE2019 compliant.
174+
def AMDGPUfmaximum3 : SDNode<"AMDGPUISD::FMAXIMUM3", SDTFPTernaryOp,
175+
[/*SDNPCommutative, SDNPAssociative*/]
176+
>;
177+
173178
// out = max(a, b, c) a, b, and c are signed ints
174179
def AMDGPUsmax3 : SDNode<"AMDGPUISD::SMAX3", AMDGPUDTIntTernaryOp,
175180
[/*SDNPCommutative, SDNPAssociative*/]
@@ -185,6 +190,11 @@ def AMDGPUfmin3 : SDNode<"AMDGPUISD::FMIN3", SDTFPTernaryOp,
185190
[/*SDNPCommutative, SDNPAssociative*/]
186191
>;
187192

193+
// out = min(a, b, c) a, b and c are floats. Operation is IEEE2019 compliant.
194+
def AMDGPUfminimum3 : SDNode<"AMDGPUISD::FMINIMUM3", SDTFPTernaryOp,
195+
[/*SDNPCommutative, SDNPAssociative*/]
196+
>;
197+
188198
// out = min(a, b, c) a, b and c are signed ints
189199
def AMDGPUsmin3 : SDNode<"AMDGPUISD::SMIN3", AMDGPUDTIntTernaryOp,
190200
[/*SDNPCommutative, SDNPAssociative*/]

‎llvm/lib/Target/AMDGPU/AMDGPUInstructions.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -252,6 +252,8 @@ def umin_oneuse : HasOneUseBinOp<umin>;
252252

253253
def fminnum_oneuse : HasOneUseBinOp<fminnum>;
254254
def fmaxnum_oneuse : HasOneUseBinOp<fmaxnum>;
255+
def fminimum_oneuse : HasOneUseBinOp<fminimum>;
256+
def fmaximum_oneuse : HasOneUseBinOp<fmaximum>;
255257

256258
def fminnum_ieee_oneuse : HasOneUseBinOp<fminnum_ieee>;
257259
def fmaxnum_ieee_oneuse : HasOneUseBinOp<fmaxnum_ieee>;

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Lines changed: 16 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1959,20 +1959,25 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
19591959
.widenScalarToNextPow2(0)
19601960
.scalarize(0);
19611961

1962-
getActionDefinitionsBuilder({
1963-
// TODO: Verify V_BFI_B32 is generated from expanded bit ops
1964-
G_FCOPYSIGN,
1962+
getActionDefinitionsBuilder(
1963+
{// TODO: Verify V_BFI_B32 is generated from expanded bit ops
1964+
G_FCOPYSIGN,
19651965

1966-
G_ATOMIC_CMPXCHG_WITH_SUCCESS,
1967-
G_ATOMICRMW_NAND,
1968-
G_ATOMICRMW_FSUB,
1969-
G_READ_REGISTER,
1970-
G_WRITE_REGISTER,
1966+
G_ATOMIC_CMPXCHG_WITH_SUCCESS, G_ATOMICRMW_NAND, G_ATOMICRMW_FSUB,
1967+
G_READ_REGISTER, G_WRITE_REGISTER,
19711968

1972-
G_SADDO, G_SSUBO,
1969+
G_SADDO, G_SSUBO})
1970+
.lower();
19731971

1974-
// TODO: Implement
1975-
G_FMINIMUM, G_FMAXIMUM}).lower();
1972+
if (ST.hasIEEEMinMax()) {
1973+
getActionDefinitionsBuilder({G_FMINIMUM, G_FMAXIMUM})
1974+
.legalFor(FPTypesPK16)
1975+
.clampMaxNumElements(0, S16, 2)
1976+
.scalarize(0);
1977+
} else {
1978+
// TODO: Implement
1979+
getActionDefinitionsBuilder({G_FMINIMUM, G_FMAXIMUM}).lower();
1980+
}
19761981

19771982
getActionDefinitionsBuilder({G_MEMCPY, G_MEMCPY_INLINE, G_MEMMOVE, G_MEMSET})
19781983
.lower();

‎llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3727,14 +3727,17 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
37273727
case AMDGPU::G_INTRINSIC_ROUNDEVEN:
37283728
case AMDGPU::G_FMINNUM:
37293729
case AMDGPU::G_FMAXNUM:
3730+
case AMDGPU::G_FMINIMUM:
3731+
case AMDGPU::G_FMAXIMUM:
37303732
case AMDGPU::G_INTRINSIC_TRUNC:
37313733
case AMDGPU::G_STRICT_FADD:
37323734
case AMDGPU::G_STRICT_FSUB:
37333735
case AMDGPU::G_STRICT_FMUL:
37343736
case AMDGPU::G_STRICT_FMA: {
3735-
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
3736-
if (Subtarget.hasSALUFloatInsts() && (Size == 32 || Size == 16) &&
3737-
isSALUMapping(MI))
3737+
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
3738+
unsigned Size = Ty.getSizeInBits();
3739+
if (Subtarget.hasSALUFloatInsts() && Ty.isScalar() &&
3740+
(Size == 32 || Size == 16) && isSALUMapping(MI))
37383741
return getDefaultMappingSOP(MI);
37393742
return getDefaultMappingVOP(MI);
37403743
}

‎llvm/lib/Target/AMDGPU/GCNSubtarget.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1218,6 +1218,9 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
12181218
// \returns true if the target has IEEE kernel descriptor mode bit
12191219
bool hasIEEEMode() const { return getGeneration() < GFX12; }
12201220

1221+
// \returns true if the target has IEEE fminimum/fmaximum instructions
1222+
bool hasIEEEMinMax() const { return getGeneration() >= GFX12; }
1223+
12211224
// \returns true if the target has WG_RR_MODE kernel descriptor mode bit
12221225
bool hasRrWGMode() const { return getGeneration() >= GFX12; }
12231226

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 23 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -763,6 +763,10 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
763763
if (Subtarget->hasMad64_32())
764764
setOperationAction({ISD::SMUL_LOHI, ISD::UMUL_LOHI}, MVT::i32, Custom);
765765

766+
if (Subtarget->hasIEEEMinMax())
767+
setOperationAction({ISD::FMAXIMUM, ISD::FMINIMUM},
768+
{MVT::f16, MVT::f32, MVT::f64, MVT::v2f16}, Legal);
769+
766770
setOperationAction(ISD::INTRINSIC_WO_CHAIN,
767771
{MVT::Other, MVT::f32, MVT::v4f32, MVT::i16, MVT::f16,
768772
MVT::v2i16, MVT::v2f16, MVT::i128},
@@ -800,6 +804,8 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
800804
ISD::FMAXNUM,
801805
ISD::FMINNUM_IEEE,
802806
ISD::FMAXNUM_IEEE,
807+
ISD::FMINIMUM,
808+
ISD::FMAXIMUM,
803809
ISD::FMA,
804810
ISD::SMIN,
805811
ISD::SMAX,
@@ -11786,10 +11792,14 @@ bool SITargetLowering::isCanonicalized(SelectionDAG &DAG, SDValue Op,
1178611792
case ISD::FMAXNUM:
1178711793
case ISD::FMINNUM_IEEE:
1178811794
case ISD::FMAXNUM_IEEE:
11795+
case ISD::FMINIMUM:
11796+
case ISD::FMAXIMUM:
1178911797
case AMDGPUISD::CLAMP:
1179011798
case AMDGPUISD::FMED3:
1179111799
case AMDGPUISD::FMAX3:
11792-
case AMDGPUISD::FMIN3: {
11800+
case AMDGPUISD::FMIN3:
11801+
case AMDGPUISD::FMAXIMUM3:
11802+
case AMDGPUISD::FMINIMUM3: {
1179311803
// FIXME: Shouldn't treat the generic operations different based these.
1179411804
// However, we aren't really required to flush the result from
1179511805
// minnum/maxnum..
@@ -11943,7 +11953,9 @@ bool SITargetLowering::isCanonicalized(Register Reg, MachineFunction &MF,
1194311953
case AMDGPU::G_FMINNUM:
1194411954
case AMDGPU::G_FMAXNUM:
1194511955
case AMDGPU::G_FMINNUM_IEEE:
11946-
case AMDGPU::G_FMAXNUM_IEEE: {
11956+
case AMDGPU::G_FMAXNUM_IEEE:
11957+
case AMDGPU::G_FMINIMUM:
11958+
case AMDGPU::G_FMAXIMUM: {
1194711959
if (Subtarget->supportsMinMaxDenormModes() ||
1194811960
// FIXME: denormalsEnabledForType is broken for dynamic
1194911961
denormalsEnabledForType(MRI.getType(Reg), MF))
@@ -12131,13 +12143,17 @@ static unsigned minMaxOpcToMin3Max3Opc(unsigned Opc) {
1213112143
case ISD::FMAXNUM:
1213212144
case ISD::FMAXNUM_IEEE:
1213312145
return AMDGPUISD::FMAX3;
12146+
case ISD::FMAXIMUM:
12147+
return AMDGPUISD::FMAXIMUM3;
1213412148
case ISD::SMAX:
1213512149
return AMDGPUISD::SMAX3;
1213612150
case ISD::UMAX:
1213712151
return AMDGPUISD::UMAX3;
1213812152
case ISD::FMINNUM:
1213912153
case ISD::FMINNUM_IEEE:
1214012154
return AMDGPUISD::FMIN3;
12155+
case ISD::FMINIMUM:
12156+
return AMDGPUISD::FMINIMUM3;
1214112157
case ISD::SMIN:
1214212158
return AMDGPUISD::SMIN3;
1214312159
case ISD::UMIN:
@@ -12497,7 +12513,9 @@ SDValue SITargetLowering::performExtractVectorEltCombine(
1249712513
case ISD::FMAXNUM:
1249812514
case ISD::FMINNUM:
1249912515
case ISD::FMAXNUM_IEEE:
12500-
case ISD::FMINNUM_IEEE: {
12516+
case ISD::FMINNUM_IEEE:
12517+
case ISD::FMAXIMUM:
12518+
case ISD::FMINIMUM: {
1250112519
SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, ResVT,
1250212520
Vec.getOperand(0), Idx);
1250312521
SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, ResVT,
@@ -13759,6 +13777,8 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
1375913777
case ISD::FMINNUM:
1376013778
case ISD::FMAXNUM_IEEE:
1376113779
case ISD::FMINNUM_IEEE:
13780+
case ISD::FMAXIMUM:
13781+
case ISD::FMINIMUM:
1376213782
case ISD::SMAX:
1376313783
case ISD::SMIN:
1376413784
case ISD::UMAX:

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5255,11 +5255,15 @@ unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) const {
52555255
case AMDGPU::S_SUB_F32: return AMDGPU::V_SUB_F32_e64;
52565256
case AMDGPU::S_MIN_F32: return AMDGPU::V_MIN_F32_e64;
52575257
case AMDGPU::S_MAX_F32: return AMDGPU::V_MAX_F32_e64;
5258+
case AMDGPU::S_MINIMUM_F32: return AMDGPU::V_MINIMUM_F32_e64;
5259+
case AMDGPU::S_MAXIMUM_F32: return AMDGPU::V_MAXIMUM_F32_e64;
52585260
case AMDGPU::S_MUL_F32: return AMDGPU::V_MUL_F32_e64;
52595261
case AMDGPU::S_ADD_F16: return AMDGPU::V_ADD_F16_fake16_e64;
52605262
case AMDGPU::S_SUB_F16: return AMDGPU::V_SUB_F16_fake16_e64;
52615263
case AMDGPU::S_MIN_F16: return AMDGPU::V_MIN_F16_fake16_e64;
52625264
case AMDGPU::S_MAX_F16: return AMDGPU::V_MAX_F16_fake16_e64;
5265+
case AMDGPU::S_MINIMUM_F16: return AMDGPU::V_MINIMUM_F16_e64;
5266+
case AMDGPU::S_MAXIMUM_F16: return AMDGPU::V_MAXIMUM_F16_e64;
52635267
case AMDGPU::S_MUL_F16: return AMDGPU::V_MUL_F16_fake16_e64;
52645268
case AMDGPU::S_CVT_PK_RTZ_F16_F32: return AMDGPU::V_CVT_PKRTZ_F16_F32_e64;
52655269
case AMDGPU::S_FMAC_F32: return AMDGPU::V_FMAC_F32_e64;
@@ -7101,6 +7105,26 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist,
71017105
Inst.eraseFromParent();
71027106
return;
71037107
}
7108+
case AMDGPU::S_MINIMUM_F32:
7109+
case AMDGPU::S_MAXIMUM_F32:
7110+
case AMDGPU::S_MINIMUM_F16:
7111+
case AMDGPU::S_MAXIMUM_F16: {
7112+
const DebugLoc &DL = Inst.getDebugLoc();
7113+
Register NewDst = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
7114+
MachineInstr *NewInstr = BuildMI(*MBB, Inst, DL, get(NewOpcode), NewDst)
7115+
.addImm(0) // src0_modifiers
7116+
.add(Inst.getOperand(1))
7117+
.addImm(0) // src1_modifiers
7118+
.add(Inst.getOperand(2))
7119+
.addImm(0) // clamp
7120+
.addImm(0); // omod
7121+
MRI.replaceRegWith(Inst.getOperand(0).getReg(), NewDst);
7122+
7123+
legalizeOperands(*NewInstr, MDT);
7124+
addUsersToMoveToVALUWorklist(NewDst, MRI, Worklist);
7125+
Inst.eraseFromParent();
7126+
return;
7127+
}
71047128
}
71057129

71067130
if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {

‎llvm/lib/Target/AMDGPU/SIInstructions.td

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3441,6 +3441,12 @@ defm : Int16Med3Pat<V_MED3_I16_e64, smin, smax>;
34413441
defm : Int16Med3Pat<V_MED3_U16_e64, umin, umax>;
34423442
} // End Predicates = [isGFX9Plus]
34433443

3444+
let OtherPredicates = [isGFX12Plus] in {
3445+
def : FPMinMaxPat<V_MINIMUMMAXIMUM_F32_e64, f32, DivergentBinFrag<fmaximum>, fminimum_oneuse>;
3446+
def : FPMinMaxPat<V_MAXIMUMMINIMUM_F32_e64, f32, DivergentBinFrag<fminimum>, fmaximum_oneuse>;
3447+
def : FPMinMaxPat<V_MINIMUMMAXIMUM_F16_e64, f16, DivergentBinFrag<fmaximum>, fminimum_oneuse>;
3448+
def : FPMinMaxPat<V_MAXIMUMMINIMUM_F16_e64, f16, DivergentBinFrag<fminimum>, fmaximum_oneuse>;
3449+
}
34443450

34453451
// Convert a floating-point power of 2 to the integer exponent.
34463452
def FPPow2ToExponentXForm : SDNodeXForm<fpimm, [{

‎llvm/lib/Target/AMDGPU/SOPInstructions.td

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -847,6 +847,15 @@ let SubtargetPredicate = HasSALUFloatInsts, mayRaiseFPException = 1,
847847
} // End SubtargetPredicate = HasSALUFloatInsts, mayRaiseFPException = 1,
848848
// Uses = [MODE], SchedRW = [WriteSFPU]
849849

850+
// On GFX12 MIN/MAX instructions do not read MODE register.
851+
let SubtargetPredicate = isGFX12Plus, mayRaiseFPException = 1, isCommutable = 1,
852+
isReMaterializable = 1, SchedRW = [WriteSFPU] in {
853+
def S_MINIMUM_F32 : SOP2_F32_Inst<"s_minimum_f32", fminimum>;
854+
def S_MAXIMUM_F32 : SOP2_F32_Inst<"s_maximum_f32", fmaximum>;
855+
def S_MINIMUM_F16 : SOP2_F16_Inst<"s_minimum_f16", fminimum>;
856+
def S_MAXIMUM_F16 : SOP2_F16_Inst<"s_maximum_f16", fmaximum>;
857+
}
858+
850859
//===----------------------------------------------------------------------===//
851860
// SOPK Instructions
852861
//===----------------------------------------------------------------------===//
@@ -2017,6 +2026,10 @@ defm S_MIN_NUM_F32 : SOP2_Real_Renamed_gfx12<0x042, S_MIN_F32, "s_min_num_f32">;
20172026
defm S_MAX_NUM_F32 : SOP2_Real_Renamed_gfx12<0x043, S_MAX_F32, "s_max_num_f32">;
20182027
defm S_MIN_NUM_F16 : SOP2_Real_Renamed_gfx12<0x04b, S_MIN_F16, "s_min_num_f16">;
20192028
defm S_MAX_NUM_F16 : SOP2_Real_Renamed_gfx12<0x04c, S_MAX_F16, "s_max_num_f16">;
2029+
defm S_MINIMUM_F32 : SOP2_Real_gfx12<0x04f>;
2030+
defm S_MAXIMUM_F32 : SOP2_Real_gfx12<0x050>;
2031+
defm S_MINIMUM_F16 : SOP2_Real_gfx12<0x051>;
2032+
defm S_MAXIMUM_F16 : SOP2_Real_gfx12<0x052>;
20202033

20212034
defm S_ADD_CO_U32 : SOP2_Real_Renamed_gfx12<0x000, S_ADD_U32, "s_add_co_u32">;
20222035
defm S_SUB_CO_U32 : SOP2_Real_Renamed_gfx12<0x001, S_SUB_U32, "s_sub_co_u32">;

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