Final

Author: JonPsson1

llvm/include/llvm/CodeGen/MachineCombinerPattern.h

@@ -34,15 +34,6 @@ enum MachineCombinerPattern : unsigned {
   REASSOC_XA_YB,
 
   TARGET_PATTERN_START
-  // SystemZ patterns.  (EXPERIMENTAL)
-  FMA2_P1P0,
-  FMA2_P0P1,
-  FMA2,
-  FMA1_Add_L,
-  FMA1_Add_R,
-  FMA3,     // These are inspired by PPC
-  FMA2_Add, //
-
 };
 
 } // end namespace llvm

llvm/lib/CodeGen/MachineCombiner.cpp

@@ -298,13 +298,6 @@ CombinerObjective MachineCombiner::getCombinerObjective(unsigned Pattern) {
   case MachineCombinerPattern::REASSOC_AX_YB:
   case MachineCombinerPattern::REASSOC_XA_BY:
   case MachineCombinerPattern::REASSOC_XA_YB:
-  case MachineCombinerPattern::FMA2_P1P0:
-  case MachineCombinerPattern::FMA2_P0P1:
-  case MachineCombinerPattern::FMA2:
-  case MachineCombinerPattern::FMA1_Add_L:
-  case MachineCombinerPattern::FMA1_Add_R:
-  case MachineCombinerPattern::FMA3:
-  case MachineCombinerPattern::FMA2_Add:
     return CombinerObjective::MustReduceDepth;
   default:
     return TII->getCombinerObjective(Pattern);

llvm/lib/Target/SystemZ/SystemZFinalizeReassociation.cpp

@@ -1,4 +1,4 @@
-//===---- SystemZFinalizeReassociation.cpp - Finalize FP reassociation ----===//
+//===----- SystemZFinalizeReassociation.cpp - Finalize reassociation ------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -11,12 +11,13 @@
 //
 // 1. Instruction selection: Disable reg/mem folding for any operations that
 //    are reassociable since MachineCombiner will not succeed otherwise.
-//    Select a reg/reg pseudo that pretends to clobber CC since the reg/mem
+//    Select a reg/reg pseudo that pretends to clobber CC if the reg/mem
 //    opcode clobbers it.
 //
-// 2. MachineCombiner: Performs reassociation with the reg/reg instructions.
+// 2. MachineCombiner: reassociation with the reg/reg instructions.
 //
-// 3. PeepholeOptimizer: Fold loads into reg/mem instructions.
+// 3. PeepholeOptimizer: Fold loads and reg/reg pseudos into reg/mem
+//                       instructions.
 //
 // 4. This pass: Convert any remaining reg/reg pseudos.
 //
@@ -33,16 +34,14 @@ namespace {
 class SystemZFinalizeReassociation : public MachineFunctionPass {
 public:
   static char ID;
-  SystemZFinalizeReassociation()
-    : MachineFunctionPass(ID), TII(nullptr) {
+  SystemZFinalizeReassociation() : MachineFunctionPass(ID), TII(nullptr) {
     initializeSystemZFinalizeReassociationPass(*PassRegistry::getPassRegistry());
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
   void getAnalysisUsage(AnalysisUsage &AU) const override;
 
 private:
-
   bool visitMBB(MachineBasicBlock &MBB);
 
   const SystemZInstrInfo *TII;
@@ -55,8 +54,8 @@ char SystemZFinalizeReassociation::ID = 0;
 INITIALIZE_PASS(SystemZFinalizeReassociation, "systemz-finalize-reassoc",
                 "SystemZ Finalize Reassociation", false, false)
 
-FunctionPass *llvm::
-createSystemZFinalizeReassociationPass(SystemZTargetMachine &TM) {
+FunctionPass *
+llvm::createSystemZFinalizeReassociationPass(SystemZTargetMachine &TM) {
   return new SystemZFinalizeReassociation();
 }
 
@@ -70,18 +69,17 @@ bool SystemZFinalizeReassociation::visitMBB(MachineBasicBlock &MBB) {
   for (MachineInstr &MI : MBB) {
     unsigned PseudoOpcode = MI.getOpcode();
     unsigned TargetOpcode =
-      PseudoOpcode == SystemZ::WFADB_CCPseudo    ? SystemZ::WFADB
-      : PseudoOpcode == SystemZ::WFASB_CCPseudo  ? SystemZ::WFASB
-      : PseudoOpcode == SystemZ::WFSDB_CCPseudo  ? SystemZ::WFSDB
-      : PseudoOpcode == SystemZ::WFSSB_CCPseudo  ? SystemZ::WFSSB
-      : PseudoOpcode == SystemZ::WFMADB_CCPseudo ? SystemZ::WFMADB
-      : PseudoOpcode == SystemZ::WFMASB_CCPseudo ? SystemZ::WFMASB
-      : 0;
+        PseudoOpcode == SystemZ::WFADB_CCPseudo   ? SystemZ::WFADB
+        : PseudoOpcode == SystemZ::WFASB_CCPseudo ? SystemZ::WFASB
+        : PseudoOpcode == SystemZ::WFSDB_CCPseudo ? SystemZ::WFSDB
+        : PseudoOpcode == SystemZ::WFSSB_CCPseudo ? SystemZ::WFSSB
+                                                  : 0;
     if (TargetOpcode) {
-        MI.setDesc(TII->get(TargetOpcode));
-        int CCIdx = MI.findRegisterDefOperandIdx(SystemZ::CC);
-        MI.removeOperand(CCIdx);
-        Changed = true;
+      MI.setDesc(TII->get(TargetOpcode));
+      int CCIdx = MI.findRegisterDefOperandIdx(SystemZ::CC, /*isDead=*/true);
+      assert(CCIdx != -1 && "Expected dead CC-def.");
+      MI.removeOperand(CCIdx);
+      Changed = true;
     }
   }
   return Changed;

llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp

@@ -2053,8 +2053,7 @@ bool SystemZDAGToDAGISel::shouldSelectForReassoc(SDNode *N) const {
   EVT VT = N->getValueType(0);
   assert(VT.isFloatingPoint() && "Expected FP SDNode");
   return N->getFlags().hasAllowReassociation() &&
-         N->getFlags().hasNoSignedZeros() &&
-         Subtarget->hasVector() &&
+         N->getFlags().hasNoSignedZeros() && Subtarget->hasVector() &&
          (VT != MVT::f32 || Subtarget->hasVectorEnhancements1()) &&
          !N->isStrictFPOpcode();
 }

llvm/lib/Target/SystemZ/SystemZInstrFP.td

@@ -501,10 +501,8 @@ let Uses = [FPC], mayRaiseFPException = 1 in {
   def MAEBR : TernaryRRD<"maebr", 0xB30E, z_any_fma, FP32, FP32>;
   def MADBR : TernaryRRD<"madbr", 0xB31E, z_any_fma, FP64, FP64>;
 
-  defm MAEB : TernaryRXFAndPseudo<"maeb", 0xED0E, z_any_fma_noreassoc, FP32,
-                                  FP32, z_load, 4>;
-  defm MADB : TernaryRXFAndPseudo<"madb", 0xED1E, z_any_fma_noreassoc, FP64,
-                                  FP64, z_load, 8>;
+  defm MAEB : TernaryRXFAndPseudo<"maeb", 0xED0E, z_any_fma, FP32, FP32, z_load, 4>;
+  defm MADB : TernaryRXFAndPseudo<"madb", 0xED1E, z_any_fma, FP64, FP64, z_load, 8>;
 }
 
 // Fused multiply-subtract.

llvm/lib/Target/SystemZ/SystemZInstrFormats.td

@@ -5537,6 +5537,9 @@ multiclass StringRRE<string mnemonic, bits<16> opcode,
                                                  GR32:$char))]>;
 }
 
+// Duplicate the instruction with a pseudo that defines CC that will be
+// selected in cases where reassociation is enabled. The CC operand is needed
+// in order to do later reg/mem folding into instructions that clobber CC.
 multiclass BinaryVRRcAndCCPseudo<string mnemonic, bits<16> opcode,
                                  SDPatternOperator operator,
                                  SDPatternOperator reassoc_operator,
@@ -5551,19 +5554,3 @@ multiclass BinaryVRRcAndCCPseudo<string mnemonic, bits<16> opcode,
                                  (reassoc_operator (tr2.vt tr2.op:$V2),
                                                    (tr2.vt tr2.op:$V3)))]>;
 }
-
-multiclass TernaryVRReAndCCPseudo<string mnemonic, bits<16> opcode,
-                                  SDPatternOperator operator,
-                                  SDPatternOperator reassoc_operator,
-                                  TypedReg tr1, TypedReg tr2, bits<4> m5 = 0,
-                                  bits<4> type = 0, string fp_mnemonic = ""> {
-  def "" : TernaryVRRe<mnemonic, opcode, operator, tr1, tr2, m5, type,
-                       fp_mnemonic>;
-  let Defs = [CC], AddedComplexity = 1 in // Win over "".
-    def _CCPseudo : Pseudo<(outs tr1.op:$V1),
-                           (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
-                           [(set (tr1.vt tr1.op:$V1),
-                                 (reassoc_operator (tr2.vt tr2.op:$V2),
-                                                   (tr2.vt tr2.op:$V3),
-                                                   (tr1.vt tr1.op:$V4)))]>;
-}