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[ValueTracking] Infer knownbits from fp classes
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6 files changed

+67
-57
lines changed

6 files changed

+67
-57
lines changed

‎llvm/include/llvm/Analysis/ValueTracking.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -259,6 +259,11 @@ struct KnownFPClass {
259259
return (KnownFPClasses & Mask) == fcNone;
260260
}
261261

262+
/// Return true if it's known this can only be one of the mask entries.
263+
bool isKnownOnly(FPClassTest Mask) const {
264+
return (KnownFPClasses & ~Mask) == fcNone;
265+
}
266+
262267
bool isUnknown() const {
263268
return KnownFPClasses == fcAllFlags && !SignBit;
264269
}

‎llvm/lib/Analysis/ValueTracking.cpp

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1111,6 +1111,40 @@ static void computeKnownBitsFromOperator(const Operator *I,
11111111
break;
11121112
}
11131113

1114+
Value *V;
1115+
// Handle bitcast from floating point to integer.
1116+
if (match(const_cast<Operator *>(I), m_ElementWiseBitCast(m_Value(V))) &&
1117+
V->getType()->isFPOrFPVectorTy()) {
1118+
KnownFPClass Result = computeKnownFPClass(V, fcAllFlags, Depth + 1, Q);
1119+
if (Result.SignBit) {
1120+
if (*Result.SignBit)
1121+
Known.makeNegative();
1122+
else
1123+
Known.makeNonNegative();
1124+
}
1125+
1126+
Type *FPType = V->getType()->getScalarType();
1127+
if (FPType->isIEEELikeFPTy()) {
1128+
int MantissaWidth = FPType->getFPMantissaWidth();
1129+
if (MantissaWidth != -1) {
1130+
if (Result.isKnownOnly(fcInf)) {
1131+
Known.Zero.setLowBits(MantissaWidth);
1132+
Known.One.setBits(MantissaWidth, BitWidth - 1);
1133+
} else if (Result.isKnownOnly(fcZero)) {
1134+
Known.Zero.setLowBits(BitWidth - 1);
1135+
} else if (Result.isKnownOnly(fcInf | fcNan)) {
1136+
Known.One.setBits(MantissaWidth, BitWidth - 1);
1137+
} else if (Result.isKnownOnly(fcSubnormal | fcZero)) {
1138+
Known.Zero.setBits(MantissaWidth, BitWidth - 1);
1139+
} else if (Result.isKnownOnly(fcInf | fcZero)) {
1140+
Known.Zero.setLowBits(MantissaWidth);
1141+
}
1142+
}
1143+
}
1144+
1145+
break;
1146+
}
1147+
11141148
// Handle cast from vector integer type to scalar or vector integer.
11151149
auto *SrcVecTy = dyn_cast<FixedVectorType>(SrcTy);
11161150
if (!SrcVecTy || !SrcVecTy->getElementType()->isIntegerTy() ||

‎llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2216,7 +2216,7 @@ define float @test_pow_afn_nnan_ninf_f32_known_integral_sitofp(float %x, i32 %y)
22162216
; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32
22172217
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]]
22182218
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[__EXP2]] to i32
2219-
; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[__POW_SIGN]], [[TMP3]]
2219+
; CHECK-NEXT: [[TMP4:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP3]]
22202220
; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP4]] to float
22212221
; CHECK-NEXT: ret float [[TMP5]]
22222222
;
@@ -2304,7 +2304,7 @@ define float @test_pow_afn_nnan_ninf_f32_known_integral_uitofp(float %x, i32 %y)
23042304
; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32
23052305
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]]
23062306
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[__EXP2]] to i32
2307-
; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[__POW_SIGN]], [[TMP3]]
2307+
; CHECK-NEXT: [[TMP4:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP3]]
23082308
; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP4]] to float
23092309
; CHECK-NEXT: ret float [[TMP5]]
23102310
;
@@ -2353,7 +2353,7 @@ define float @test_pow_afn_nnan_ninf_f32_known_integral_uitofp_i256(float %x, i2
23532353
; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32
23542354
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]]
23552355
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[__EXP2]] to i32
2356-
; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[__POW_SIGN]], [[TMP3]]
2356+
; CHECK-NEXT: [[TMP4:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP3]]
23572357
; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP4]] to float
23582358
; CHECK-NEXT: ret float [[TMP5]]
23592359
;
@@ -2376,7 +2376,7 @@ define float @test_pow_afn_nnan_ninf_f32_known_integral_sitofp_i256(float %x, i2
23762376
; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32
23772377
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]]
23782378
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[__EXP2]] to i32
2379-
; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[__POW_SIGN]], [[TMP3]]
2379+
; CHECK-NEXT: [[TMP4:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP3]]
23802380
; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP4]] to float
23812381
; CHECK-NEXT: ret float [[TMP5]]
23822382
;
@@ -2399,7 +2399,7 @@ define <2 x float> @test_pow_afn_nnan_ninf_v2f32_known_integral_sitofp(<2 x floa
23992399
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x float> [[X]] to <2 x i32>
24002400
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i32> [[__YEVEN]], [[TMP2]]
24012401
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x float> [[__EXP2]] to <2 x i32>
2402-
; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i32> [[__POW_SIGN]], [[TMP3]]
2402+
; CHECK-NEXT: [[TMP4:%.*]] = or disjoint <2 x i32> [[__POW_SIGN]], [[TMP3]]
24032403
; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP4]] to <2 x float>
24042404
; CHECK-NEXT: ret <2 x float> [[TMP5]]
24052405
;
@@ -2448,7 +2448,7 @@ define <2 x float> @test_pow_afn_nnan_ninf_v2f32_known_integral_uitofp(<2 x floa
24482448
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x float> [[X]] to <2 x i32>
24492449
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i32> [[__YEVEN]], [[TMP2]]
24502450
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x float> [[__EXP2]] to <2 x i32>
2451-
; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i32> [[__POW_SIGN]], [[TMP3]]
2451+
; CHECK-NEXT: [[TMP4:%.*]] = or disjoint <2 x i32> [[__POW_SIGN]], [[TMP3]]
24522452
; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP4]] to <2 x float>
24532453
; CHECK-NEXT: ret <2 x float> [[TMP5]]
24542454
;
@@ -2560,7 +2560,7 @@ define float @test_pow_afn_f32_nnan_ninf__y_known_integral_trunc(float %x, float
25602560
; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32
25612561
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]]
25622562
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[__EXP2]] to i32
2563-
; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[__POW_SIGN]], [[TMP3]]
2563+
; CHECK-NEXT: [[TMP4:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP3]]
25642564
; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP4]] to float
25652565
; CHECK-NEXT: ret float [[TMP5]]
25662566
;

‎llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -680,7 +680,7 @@ define float @test_pown_afn_nnan_ninf_f32(float %x, i32 %y) {
680680
; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[X]] to i32
681681
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP0]]
682682
; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[__EXP2]] to i32
683-
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[__POW_SIGN]], [[TMP1]]
683+
; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP1]]
684684
; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float
685685
; CHECK-NEXT: ret float [[TMP3]]
686686
;
@@ -703,7 +703,7 @@ define <2 x float> @test_pown_afn_nnan_ninf_v2f32(<2 x float> %x, <2 x i32> %y)
703703
; CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[X]] to <2 x i32>
704704
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i32> [[__YEVEN]], [[TMP0]]
705705
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[__EXP2]] to <2 x i32>
706-
; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i32> [[__POW_SIGN]], [[TMP1]]
706+
; CHECK-NEXT: [[TMP2:%.*]] = or disjoint <2 x i32> [[__POW_SIGN]], [[TMP1]]
707707
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to <2 x float>
708708
; CHECK-NEXT: ret <2 x float> [[TMP3]]
709709
;
@@ -772,7 +772,7 @@ define half @test_pown_afn_nnan_ninf_f16(half %x, i32 %y) {
772772
; CHECK-NEXT: [[TMP0:%.*]] = bitcast half [[X]] to i16
773773
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i16 [[__YEVEN]], [[TMP0]]
774774
; CHECK-NEXT: [[TMP1:%.*]] = bitcast half [[__EXP2]] to i16
775-
; CHECK-NEXT: [[TMP2:%.*]] = or i16 [[__POW_SIGN]], [[TMP1]]
775+
; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i16 [[__POW_SIGN]], [[TMP1]]
776776
; CHECK-NEXT: [[TMP3:%.*]] = bitcast i16 [[TMP2]] to half
777777
; CHECK-NEXT: ret half [[TMP3]]
778778
;
@@ -795,7 +795,7 @@ define <2 x half> @test_pown_afn_nnan_ninf_v2f16(<2 x half> %x, <2 x i32> %y) {
795795
; CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x half> [[X]] to <2 x i16>
796796
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i16> [[__YEVEN]], [[TMP0]]
797797
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x half> [[__EXP2]] to <2 x i16>
798-
; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i16> [[__POW_SIGN]], [[TMP1]]
798+
; CHECK-NEXT: [[TMP2:%.*]] = or disjoint <2 x i16> [[__POW_SIGN]], [[TMP1]]
799799
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to <2 x half>
800800
; CHECK-NEXT: ret <2 x half> [[TMP3]]
801801
;
@@ -829,7 +829,7 @@ define float @test_pown_fast_f32_strictfp(float %x, i32 %y) #1 {
829829
; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[X]] to i32
830830
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP0]]
831831
; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[__EXP2]] to i32
832-
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[__POW_SIGN]], [[TMP1]]
832+
; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP1]]
833833
; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float
834834
; CHECK-NEXT: ret float [[TMP3]]
835835
;
@@ -1075,7 +1075,7 @@ define float @test_pown_afn_ninf_nnan_f32__x_known_positive(float nofpclass(ninf
10751075
; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[X]] to i32
10761076
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP0]]
10771077
; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[__EXP2]] to i32
1078-
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[__POW_SIGN]], [[TMP1]]
1078+
; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP1]]
10791079
; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float
10801080
; CHECK-NEXT: ret float [[TMP3]]
10811081
;

‎llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -360,7 +360,7 @@ declare half @_Z4pownDhi(half, i32)
360360
; GCN-NATIVE: %0 = bitcast half %x to i16
361361
; GCN-NATIVE: %__pow_sign = and i16 %__yeven, %0
362362
; GCN-NATIVE: %1 = bitcast half %__exp2 to i16
363-
; GCN-NATIVE: %2 = or i16 %__pow_sign, %1
363+
; GCN-NATIVE: %2 = or disjoint i16 %__pow_sign, %1
364364
; GCN-NATIVE: %3 = bitcast i16 %2 to half
365365
define half @test_pown_f16(half %x, i32 %y) {
366366
entry:
@@ -378,7 +378,7 @@ declare float @_Z4pownfi(float, i32)
378378
; GCN: %[[r0:.*]] = bitcast float %tmp to i32
379379
; GCN: %__pow_sign = and i32 %[[r0]], -2147483648
380380
; GCN: %[[r1:.*]] = bitcast float %__exp2 to i32
381-
; GCN: %[[r2:.*]] = or i32 %__pow_sign, %[[r1]]
381+
; GCN: %[[r2:.*]] = or disjoint i32 %__pow_sign, %[[r1]]
382382
; GCN: store i32 %[[r2]], ptr addrspace(1) %a, align 4
383383
define amdgpu_kernel void @test_pow(ptr addrspace(1) nocapture %a) {
384384
entry:
@@ -414,7 +414,7 @@ entry:
414414
; GCN: %[[r0:.*]] = bitcast float %tmp to i32
415415
; GCN: %__pow_sign = and i32 %__yeven, %[[r0]]
416416
; GCN: %[[r1:.*]] = bitcast float %__exp2 to i32
417-
; GCN: %[[r2:.*]] = or i32 %__pow_sign, %[[r1]]
417+
; GCN: %[[r2:.*]] = or disjoint i32 %__pow_sign, %[[r1]]
418418
; GCN: store i32 %[[r2]], ptr addrspace(1) %a, align 4
419419
define amdgpu_kernel void @test_pown(ptr addrspace(1) nocapture %a) {
420420
entry:
@@ -438,7 +438,7 @@ declare <2 x half> @_Z3powDv2_DhS_(<2 x half>, <2 x half>)
438438
; GCN: %1 = bitcast half %x to i16
439439
; GCN: %__pow_sign = and i16 %1, -32768
440440
; GCN: %2 = bitcast half %__exp2 to i16
441-
; GCN: %3 = or i16 %__pow_sign, %2
441+
; GCN: %3 = or disjoint i16 %__pow_sign, %2
442442
; GCN: %4 = bitcast i16 %3 to half
443443
define half @test_pow_fast_f16__y_13(half %x) {
444444
%powr = tail call fast half @_Z3powDhDh(half %x, half 13.0)
@@ -453,7 +453,7 @@ define half @test_pow_fast_f16__y_13(half %x) {
453453
; GCN: %1 = bitcast <2 x half> %x to <2 x i16>
454454
; GCN: %__pow_sign = and <2 x i16> %1, <i16 -32768, i16 -32768>
455455
; GCN: %2 = bitcast <2 x half> %__exp2 to <2 x i16>
456-
; GCN: %3 = or <2 x i16> %__pow_sign, %2
456+
; GCN: %3 = or disjoint <2 x i16> %__pow_sign, %2
457457
; GCN: %4 = bitcast <2 x i16> %3 to <2 x half>
458458
define <2 x half> @test_pow_fast_v2f16__y_13(<2 x half> %x) {
459459
%powr = tail call fast <2 x half> @_Z3powDv2_DhS_(<2 x half> %x, <2 x half> <half 13.0, half 13.0>)

‎llvm/test/Transforms/InstCombine/known-bits.ll

Lines changed: 10 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -1376,10 +1376,7 @@ define i8 @nonzero_reduce_xor_vscale_odd(<vscale x 3 x i8> %xx) {
13761376

13771377
define i1 @test_sign_pos(float %x) {
13781378
; CHECK-LABEL: @test_sign_pos(
1379-
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
1380-
; CHECK-NEXT: [[Y:%.*]] = bitcast float [[FABS]] to i32
1381-
; CHECK-NEXT: [[SIGN:%.*]] = icmp sgt i32 [[Y]], -1
1382-
; CHECK-NEXT: ret i1 [[SIGN]]
1379+
; CHECK-NEXT: ret i1 true
13831380
;
13841381
%fabs = call float @llvm.fabs.f32(float %x)
13851382
%y = bitcast float %fabs to i32
@@ -1389,11 +1386,7 @@ define i1 @test_sign_pos(float %x) {
13891386

13901387
define i1 @test_sign_neg(float %x) {
13911388
; CHECK-LABEL: @test_sign_neg(
1392-
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
1393-
; CHECK-NEXT: [[FNABS:%.*]] = fneg float [[FABS]]
1394-
; CHECK-NEXT: [[Y:%.*]] = bitcast float [[FNABS]] to i32
1395-
; CHECK-NEXT: [[SIGN:%.*]] = icmp slt i32 [[Y]], 0
1396-
; CHECK-NEXT: ret i1 [[SIGN]]
1389+
; CHECK-NEXT: ret i1 true
13971390
;
13981391
%fabs = call float @llvm.fabs.f32(float %x)
13991392
%fnabs = fneg float %fabs
@@ -1404,10 +1397,7 @@ define i1 @test_sign_neg(float %x) {
14041397

14051398
define <2 x i1> @test_sign_pos_vec(<2 x float> %x) {
14061399
; CHECK-LABEL: @test_sign_pos_vec(
1407-
; CHECK-NEXT: [[FABS:%.*]] = call <2 x float> @llvm.fabs.v2f32(<2 x float> [[X:%.*]])
1408-
; CHECK-NEXT: [[Y:%.*]] = bitcast <2 x float> [[FABS]] to <2 x i32>
1409-
; CHECK-NEXT: [[SIGN:%.*]] = icmp slt <2 x i32> [[Y]], zeroinitializer
1410-
; CHECK-NEXT: ret <2 x i1> [[SIGN]]
1400+
; CHECK-NEXT: ret <2 x i1> zeroinitializer
14111401
;
14121402
%fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %x)
14131403
%y = bitcast <2 x float> %fabs to <2 x i32>
@@ -1417,9 +1407,7 @@ define <2 x i1> @test_sign_pos_vec(<2 x float> %x) {
14171407

14181408
define i32 @test_inf_only(float nofpclass(nan sub norm zero) %x) {
14191409
; CHECK-LABEL: @test_inf_only(
1420-
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
1421-
; CHECK-NEXT: [[AND:%.*]] = bitcast float [[TMP1]] to i32
1422-
; CHECK-NEXT: ret i32 [[AND]]
1410+
; CHECK-NEXT: ret i32 2130706432
14231411
;
14241412
%y = bitcast float %x to i32
14251413
%and = and i32 %y, 2147483647
@@ -1428,9 +1416,7 @@ define i32 @test_inf_only(float nofpclass(nan sub norm zero) %x) {
14281416

14291417
define i32 @test_zero_only(float nofpclass(nan sub norm inf) %x) {
14301418
; CHECK-LABEL: @test_zero_only(
1431-
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
1432-
; CHECK-NEXT: [[AND:%.*]] = bitcast float [[TMP1]] to i32
1433-
; CHECK-NEXT: ret i32 [[AND]]
1419+
; CHECK-NEXT: ret i32 0
14341420
;
14351421
%y = bitcast float %x to i32
14361422
%and = and i32 %y, 2147483647
@@ -1450,9 +1436,7 @@ define i80 @test_zero_only_non_ieee(x86_fp80 nofpclass(nan sub norm inf) %x) {
14501436

14511437
define i32 @test_inf_nan_only(float nofpclass(sub norm zero) %x) {
14521438
; CHECK-LABEL: @test_inf_nan_only(
1453-
; CHECK-NEXT: [[Y:%.*]] = bitcast float [[X:%.*]] to i32
1454-
; CHECK-NEXT: [[AND:%.*]] = and i32 [[Y]], 2130706432
1455-
; CHECK-NEXT: ret i32 [[AND]]
1439+
; CHECK-NEXT: ret i32 2130706432
14561440
;
14571441
%y = bitcast float %x to i32
14581442
%and = and i32 %y, 2130706432
@@ -1461,9 +1445,7 @@ define i32 @test_inf_nan_only(float nofpclass(sub norm zero) %x) {
14611445

14621446
define i32 @test_sub_zero_only(float nofpclass(nan norm inf) %x) {
14631447
; CHECK-LABEL: @test_sub_zero_only(
1464-
; CHECK-NEXT: [[Y:%.*]] = bitcast float [[X:%.*]] to i32
1465-
; CHECK-NEXT: [[AND:%.*]] = and i32 [[Y]], 2130706432
1466-
; CHECK-NEXT: ret i32 [[AND]]
1448+
; CHECK-NEXT: ret i32 0
14671449
;
14681450
%y = bitcast float %x to i32
14691451
%and = and i32 %y, 2130706432
@@ -1472,9 +1454,7 @@ define i32 @test_sub_zero_only(float nofpclass(nan norm inf) %x) {
14721454

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define i32 @test_inf_zero_only(float nofpclass(nan norm sub) %x) {
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; CHECK-LABEL: @test_inf_zero_only(
1475-
; CHECK-NEXT: [[Y:%.*]] = bitcast float [[X:%.*]] to i32
1476-
; CHECK-NEXT: [[AND:%.*]] = and i32 [[Y]], 16777215
1477-
; CHECK-NEXT: ret i32 [[AND]]
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; CHECK-NEXT: ret i32 0
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;
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%y = bitcast float %x to i32
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%and = and i32 %y, 16777215
@@ -1483,11 +1463,7 @@ define i32 @test_inf_zero_only(float nofpclass(nan norm sub) %x) {
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define i1 @test_simplify_icmp(i32 %x) {
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; CHECK-LABEL: @test_simplify_icmp(
1486-
; CHECK-NEXT: [[CAST1:%.*]] = uitofp i32 [[X:%.*]] to double
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; CHECK-NEXT: [[CAST2:%.*]] = bitcast double [[CAST1]] to i64
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; CHECK-NEXT: [[MASK:%.*]] = and i64 [[CAST2]], -140737488355328
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[MASK]], -1970324836974592
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; CHECK-NEXT: ret i1 [[CMP]]
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; CHECK-NEXT: ret i1 false
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;
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%cast1 = uitofp i32 %x to double
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%cast2 = bitcast double %cast1 to i64
@@ -1502,12 +1478,7 @@ define i16 @test_simplify_mask(i32 %ui, float %x) {
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; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[CONV]], [[X:%.*]]
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; CHECK-NEXT: br i1 [[CMP]], label [[IF_ELSE:%.*]], label [[IF_END:%.*]]
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; CHECK: if.end:
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; CHECK-NEXT: [[CAST:%.*]] = bitcast float [[CONV]] to i32
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; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[CAST]], 16
1507-
; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SHR]] to i16
1508-
; CHECK-NEXT: [[AND:%.*]] = and i16 [[TRUNC]], -32768
1509-
; CHECK-NEXT: [[OR:%.*]] = or disjoint i16 [[AND]], 31744
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; CHECK-NEXT: ret i16 [[OR]]
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; CHECK-NEXT: ret i16 31744
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; CHECK: if.else:
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; CHECK-NEXT: ret i16 0
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;

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