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michaelmaitlandmichaelmaitland
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[RISCV][GISEL] Legalize G_VAARG through expansion. (#73065)
G_VAARG can be expanded similiar to SelectionDAG::expandVAArg through LegalizerHelper::lower. This patch implements the lowering through this style of expansion. The expansion gets the head of the va_list by loading the pointer to va_list. Then, the head of the list is adjusted depending on argument alignment information. This gives a pointer to the element to be read out of the va_list. Next, the head of the va_list is bumped to the next element in the list. The new head of the list is stored back to the original pointer to the head of the va_list so that subsequent G_VAARG instructions get the next element in the list. Lastly, the element is loaded from the alignment adjusted pointer constructed earlier. This change is stacked on #73062.
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‎llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

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Original file line numberDiff line numberDiff line change
@@ -432,6 +432,7 @@ class LegalizerHelper {
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LegalizeResult lowerVectorReduction(MachineInstr &MI);
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LegalizeResult lowerMemcpyInline(MachineInstr &MI);
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LegalizeResult lowerMemCpyFamily(MachineInstr &MI, unsigned MaxLen = 0);
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LegalizeResult lowerVAArg(MachineInstr &MI);
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};
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/// Helper function that creates a libcall to the given \p Name using the given

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3793,6 +3793,8 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
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return lowerTRUNC(MI);
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GISEL_VECREDUCE_CASES_NONSEQ
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return lowerVectorReduction(MI);
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case G_VAARG:
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return lowerVAArg(MI);
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}
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}
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@@ -7887,6 +7889,56 @@ LegalizerHelper::lowerVectorReduction(MachineInstr &MI) {
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return UnableToLegalize;
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}
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static Type *getTypeForLLT(LLT Ty, LLVMContext &C);
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LegalizerHelper::LegalizeResult LegalizerHelper::lowerVAArg(MachineInstr &MI) {
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MachineFunction &MF = *MI.getMF();
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const DataLayout &DL = MIRBuilder.getDataLayout();
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LLVMContext &Ctx = MF.getFunction().getContext();
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Register ListPtr = MI.getOperand(1).getReg();
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LLT PtrTy = MRI.getType(ListPtr);
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// LstPtr is a pointer to the head of the list. Get the address
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// of the head of the list.
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Align PtrAlignment = DL.getABITypeAlign(getTypeForLLT(PtrTy, Ctx));
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MachineMemOperand *PtrLoadMMO = MF.getMachineMemOperand(
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MachinePointerInfo(), MachineMemOperand::MOLoad, PtrTy, PtrAlignment);
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auto VAList = MIRBuilder.buildLoad(PtrTy, ListPtr, *PtrLoadMMO).getReg(0);
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const Align A(MI.getOperand(2).getImm());
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LLT PtrTyAsScalarTy = LLT::scalar(PtrTy.getSizeInBits());
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if (A > TLI.getMinStackArgumentAlignment()) {
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Register AlignAmt =
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MIRBuilder.buildConstant(PtrTyAsScalarTy, A.value() - 1).getReg(0);
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auto AddDst = MIRBuilder.buildPtrAdd(PtrTy, VAList, AlignAmt);
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auto AndDst = MIRBuilder.buildMaskLowPtrBits(PtrTy, AddDst, Log2(A));
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VAList = AndDst.getReg(0);
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}
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// Increment the pointer, VAList, to the next vaarg
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// The list should be bumped by the size of element in the current head of
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// list.
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Register Dst = MI.getOperand(0).getReg();
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LLT LLTTy = MRI.getType(Dst);
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Type *Ty = getTypeForLLT(LLTTy, Ctx);
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auto IncAmt =
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MIRBuilder.buildConstant(PtrTyAsScalarTy, DL.getTypeAllocSize(Ty));
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auto Succ = MIRBuilder.buildPtrAdd(PtrTy, VAList, IncAmt);
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// Store the increment VAList to the legalized pointer
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MachineMemOperand *StoreMMO = MF.getMachineMemOperand(
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MachinePointerInfo(), MachineMemOperand::MOStore, PtrTy, PtrAlignment);
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MIRBuilder.buildStore(Succ, ListPtr, *StoreMMO);
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// Load the actual argument out of the pointer VAList
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Align EltAlignment = DL.getABITypeAlign(Ty);
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MachineMemOperand *EltLoadMMO = MF.getMachineMemOperand(
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MachinePointerInfo(), MachineMemOperand::MOLoad, LLTTy, EltAlignment);
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MIRBuilder.buildLoad(Dst, VAList, *EltLoadMMO);
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MI.eraseFromParent();
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return Legalized;
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}
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static bool shouldLowerMemFuncForSize(const MachineFunction &MF) {
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// On Darwin, -Os means optimize for size without hurting performance, so
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// only really optimize for size when -Oz (MinSize) is used.

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -317,6 +317,14 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
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getActionDefinitionsBuilder(G_VASTART).customFor({p0});
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// va_list must be a pointer, but most sized types are pretty easy to handle
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// as the destination.
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getActionDefinitionsBuilder(G_VAARG)
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// TODO: Implement narrowScalar and widenScalar for G_VAARG for types
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// outside the [s32, sXLen] range.
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.clampScalar(0, s32, sXLen)
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.lowerForCartesianProduct({s32, sXLen, p0}, {p0});
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getLegacyLegalizerInfo().computeTables();
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}
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‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-vaarg-rv32.mir

Lines changed: 70 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,70 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - | FileCheck %s
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# On RISC-V, the MinStackArgumentAlignment is 1 and the ABI Alignment for p0 is
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# greater than 1, so we will always generate code to adjust for this alignment.
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---
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name: va_arg_i32
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legalized: false
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tracksRegLiveness: true
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fixedStack:
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- { id: 0, type: default, offset: 0, size: 4, alignment: 16,
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isImmutable: true, isAliased: false }
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stack:
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- { id: 0, type: default, offset: 0, size: 4, alignment: 4 }
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machineFunctionInfo:
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varArgsFrameIndex: -1
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varArgsSaveSize: 0
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body: |
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bb.1:
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liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
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; CHECK-LABEL: name: va_arg_i32
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; CHECK: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0))
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
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; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD]], [[C]](s32)
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -4
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; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[PTR_ADD]], [[C1]](s32)
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTRMASK]], [[C2]](s32)
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; CHECK-NEXT: G_STORE [[PTR_ADD1]](p0), [[FRAME_INDEX]](p0) :: (store (p0))
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; CHECK-NEXT: PseudoRET
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%0:_(p0) = G_FRAME_INDEX %stack.0
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%1:_(s32) = G_VAARG %0(p0), 4
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PseudoRET
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...
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---
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name: va_arg_ptr
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legalized: false
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tracksRegLiveness: true
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fixedStack:
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- { id: 0, type: default, offset: 0, size: 4, alignment: 16,
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isImmutable: true, isAliased: false }
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stack:
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- { id: 0, type: default, offset: 0, size: 4, alignment: 4 }
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machineFunctionInfo:
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varArgsFrameIndex: -1
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varArgsSaveSize: 0
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body: |
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bb.1:
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liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
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; CHECK-LABEL: name: va_arg_ptr
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; CHECK: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0))
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
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; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD]], [[C]](s32)
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -4
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; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[PTR_ADD]], [[C1]](s32)
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTRMASK]], [[C2]](s32)
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; CHECK-NEXT: G_STORE [[PTR_ADD1]](p0), [[FRAME_INDEX]](p0) :: (store (p0))
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; CHECK-NEXT: PseudoRET
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%0:_(p0) = G_FRAME_INDEX %stack.0
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%1:_(p0) = G_VAARG %0(p0), 4
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PseudoRET
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...

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-vaarg-rv64.mir

Lines changed: 93 additions & 0 deletions
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@@ -0,0 +1,93 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - | FileCheck %s
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4+
# On RISC-V, the MinStackArgumentAlignment is 1 and the ABI Alignment for p0 is
5+
# greater than 1, so we will always generate code to adjust for this alignment.
6+
7+
---
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name: va_arg_i32
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legalized: false
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tracksRegLiveness: true
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fixedStack:
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- { id: 0, type: default, offset: 0, size: 8, alignment: 16,
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isImmutable: true, isAliased: false }
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stack:
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- { id: 0, type: default, offset: 0, size: 8, alignment: 8 }
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machineFunctionInfo:
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varArgsFrameIndex: -1
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varArgsSaveSize: 0
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body: |
20+
bb.1:
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; CHECK-LABEL: name: va_arg_i32
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; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0))
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
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; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD]], [[C]](s64)
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4
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; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[PTR_ADD]], [[C1]](s64)
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
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; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTRMASK]], [[C2]](s64)
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; CHECK-NEXT: G_STORE [[PTR_ADD1]](p0), [[FRAME_INDEX]](p0) :: (store (p0))
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; CHECK-NEXT: PseudoRET
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%0:_(p0) = G_FRAME_INDEX %stack.0
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%1:_(s32) = G_VAARG %0(p0), 4
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PseudoRET
35+
...
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---
37+
name: va_arg_i64
38+
legalized: false
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tracksRegLiveness: true
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fixedStack:
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- { id: 0, type: default, offset: 0, size: 8, alignment: 16,
42+
isImmutable: true, isAliased: false }
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stack:
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- { id: 0, type: default, offset: 0, size: 8, alignment: 8 }
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machineFunctionInfo:
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varArgsFrameIndex: -1
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varArgsSaveSize: 0
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body: |
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bb.1:
50+
; CHECK-LABEL: name: va_arg_i64
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; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0))
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
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; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD]], [[C]](s64)
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4
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; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[PTR_ADD]], [[C1]](s64)
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
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; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTRMASK]], [[C2]](s64)
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; CHECK-NEXT: G_STORE [[PTR_ADD1]](p0), [[FRAME_INDEX]](p0) :: (store (p0))
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; CHECK-NEXT: PseudoRET
61+
%0:_(p0) = G_FRAME_INDEX %stack.0
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%1:_(s64) = G_VAARG %0(p0), 4
63+
PseudoRET
64+
...
65+
---
66+
name: va_arg_ptr
67+
legalized: false
68+
tracksRegLiveness: true
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fixedStack:
70+
- { id: 0, type: default, offset: 0, size: 8, alignment: 16,
71+
isImmutable: true, isAliased: false }
72+
stack:
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- { id: 0, type: default, offset: 0, size: 8, alignment: 8 }
74+
machineFunctionInfo:
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varArgsFrameIndex: -1
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varArgsSaveSize: 0
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body: |
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bb.1:
79+
; CHECK-LABEL: name: va_arg_ptr
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; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0))
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
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; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD]], [[C]](s64)
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4
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; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[PTR_ADD]], [[C1]](s64)
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
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; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTRMASK]], [[C2]](s64)
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; CHECK-NEXT: G_STORE [[PTR_ADD1]](p0), [[FRAME_INDEX]](p0) :: (store (p0))
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; CHECK-NEXT: PseudoRET
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%0:_(p0) = G_FRAME_INDEX %stack.0
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%1:_(s64) = G_VAARG %0(p0), 4
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PseudoRET
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...

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