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mmhammha
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Review feedback: Remove dead code, add OGCG tests
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6 files changed

+161
-169
lines changed

6 files changed

+161
-169
lines changed

‎clang/lib/CIR/CodeGen/CIRGenExpr.cpp

Lines changed: 0 additions & 87 deletions
Original file line numberDiff line numberDiff line change
@@ -1197,93 +1197,6 @@ Address CIRGenFunction::emitArrayToPointerDecay(const Expr *e) {
11971197
return Address(ptr, addr.getAlignment());
11981198
}
11991199

1200-
/// Emit the operand of a glvalue conditional operator. This is either a glvalue
1201-
/// or a (possibly-parenthesized) throw-expression. If this is a throw, no
1202-
/// LValue is returned and the current block has been terminated.
1203-
static std::optional<LValue> emitLValueOrThrowExpression(CIRGenFunction &cgf,
1204-
const Expr *operand) {
1205-
if (isa<CXXThrowExpr>(operand->IgnoreParens())) {
1206-
assert(!cir::MissingFeatures::throwOp());
1207-
cgf.cgm.errorNYI(operand->getSourceRange(),
1208-
"throw expressions in conditional operator");
1209-
return std::nullopt;
1210-
}
1211-
1212-
return cgf.emitLValue(operand);
1213-
}
1214-
1215-
// Create and generate the 3 blocks for a conditional operator.
1216-
// Leaves the 'current block' in the continuation basic block.
1217-
template <typename FuncTy>
1218-
CIRGenFunction::ConditionalInfo
1219-
CIRGenFunction::emitConditionalBlocks(const AbstractConditionalOperator *e,
1220-
const FuncTy &branchGenFunc) {
1221-
ConditionalInfo info;
1222-
CIRGenFunction &cgf = *this;
1223-
ConditionalEvaluation eval(cgf);
1224-
mlir::Location loc = cgf.getLoc(e->getSourceRange());
1225-
Expr *trueExpr = e->getTrueExpr();
1226-
Expr *falseExpr = e->getFalseExpr();
1227-
1228-
mlir::Value condV = cgf.emitOpOnBoolExpr(loc, e->getCond());
1229-
SmallVector<mlir::OpBuilder::InsertPoint, 2> insertPoints{};
1230-
mlir::Type yieldTy{};
1231-
1232-
auto emitBranch = [&](mlir::OpBuilder &b, mlir::Location loc, Expr *expr,
1233-
std::optional<LValue> &branchInfo) {
1234-
CIRGenFunction::LexicalScope lexScope{cgf, loc, b.getInsertionBlock()};
1235-
cgf.curLexScope->setAsTernary();
1236-
1237-
assert(!cir::MissingFeatures::incrementProfileCounter());
1238-
eval.beginEvaluation();
1239-
branchInfo = branchGenFunc(cgf, expr);
1240-
mlir::Value branch = branchInfo->getPointer();
1241-
eval.endEvaluation();
1242-
1243-
if (branch) {
1244-
yieldTy = branch.getType();
1245-
b.create<cir::YieldOp>(loc, branch);
1246-
} else {
1247-
// If LHS or RHS is a throw or void expression we need to patch
1248-
// arms as to properly match yield types.
1249-
insertPoints.push_back(b.saveInsertionPoint());
1250-
}
1251-
};
1252-
1253-
info.result = builder
1254-
.create<cir::TernaryOp>(
1255-
loc, condV, /*trueBuilder=*/
1256-
[&](mlir::OpBuilder &b, mlir::Location loc) {
1257-
emitBranch(b, loc, trueExpr, info.lhs);
1258-
},
1259-
/*falseBuilder=*/
1260-
[&](mlir::OpBuilder &b, mlir::Location loc) {
1261-
emitBranch(b, loc, falseExpr, info.rhs);
1262-
})
1263-
.getResult();
1264-
1265-
if (!insertPoints.empty()) {
1266-
// If both arms are void, so be it.
1267-
if (!yieldTy)
1268-
yieldTy = cgf.VoidTy;
1269-
1270-
// Insert required yields.
1271-
for (mlir::OpBuilder::InsertPoint &toInsert : insertPoints) {
1272-
mlir::OpBuilder::InsertionGuard guard(builder);
1273-
builder.restoreInsertionPoint(toInsert);
1274-
1275-
// Block does not return: build empty yield.
1276-
if (mlir::isa<cir::VoidType>(yieldTy)) {
1277-
builder.create<cir::YieldOp>(loc);
1278-
} else { // Block returns: set null yield value.
1279-
mlir::Value op0 = builder.getNullValue(yieldTy, loc);
1280-
builder.create<cir::YieldOp>(loc, op0);
1281-
}
1282-
}
1283-
}
1284-
return info;
1285-
}
1286-
12871200
/// Emit an `if` on a boolean condition, filling `then` and `else` into
12881201
/// appropriated regions.
12891202
mlir::LogicalResult CIRGenFunction::emitIfOnBoolExpr(const Expr *cond,

‎clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -949,7 +949,7 @@ class ScalarExprEmitter : public StmtVisitor<ScalarExprEmitter, mlir::Value> {
949949
return {};
950950
}
951951

952-
bool instrumentRegions = cgf.cgm.getCodeGenOpts().hasProfileClangInstr();
952+
assert(!cir::MissingFeatures::instrumentation());
953953
mlir::Type resTy = cgf.convertType(e->getType());
954954
mlir::Location loc = cgf.getLoc(e->getExprLoc());
955955

@@ -981,7 +981,7 @@ class ScalarExprEmitter : public StmtVisitor<ScalarExprEmitter, mlir::Value> {
981981
return {};
982982
}
983983

984-
bool instrumentRegions = cgf.cgm.getCodeGenOpts().hasProfileClangInstr();
984+
assert(!cir::MissingFeatures::instrumentation());
985985
mlir::Type resTy = cgf.convertType(e->getType());
986986
mlir::Location loc = cgf.getLoc(e->getExprLoc());
987987

@@ -1930,7 +1930,7 @@ mlir::Value ScalarExprEmitter::VisitAbstractConditionalOperator(
19301930
// If the condition constant folds and can be elided, try to avoid emitting
19311931
// the condition and the dead arm.
19321932
bool condExprBool;
1933-
if (cgf.constantFoldsToSimpleInteger(condExpr, condExprBool)) {
1933+
if (cgf.constantFoldsToBool(condExpr, condExprBool)) {
19341934
Expr *live = lhsExpr, *dead = rhsExpr;
19351935
if (!condExprBool)
19361936
std::swap(live, dead);

‎clang/lib/CIR/CodeGen/CIRGenFunction.cpp

Lines changed: 0 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -200,20 +200,6 @@ bool CIRGenFunction::constantFoldsToSimpleInteger(const Expr *cond,
200200
return true;
201201
}
202202

203-
/// If the specified expression does not fold
204-
/// to a constant, or if it does but contains a label, return false. If it
205-
/// constant folds return true and set the boolean result in `resultBool`.
206-
bool CIRGenFunction::constantFoldsToSimpleInteger(const Expr *cond,
207-
bool &resultBool,
208-
bool allowLabels) {
209-
llvm::APSInt resultInt;
210-
if (!constantFoldsToSimpleInteger(cond, resultInt, allowLabels))
211-
return false;
212-
213-
resultBool = resultInt.getBoolValue();
214-
return true;
215-
}
216-
217203
void CIRGenFunction::emitAndUpdateRetAlloca(QualType type, mlir::Location loc,
218204
CharUnits alignment) {
219205
if (!type->isVoidType()) {

‎clang/lib/CIR/CodeGen/CIRGenFunction.h

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -117,14 +117,6 @@ class CIRGenFunction : public CIRGenTypeCache {
117117
llvm::DenseMap<const OpaqueValueExpr *, LValue> opaqueLValues;
118118
llvm::DenseMap<const OpaqueValueExpr *, RValue> opaqueRValues;
119119

120-
// This keeps track of the associated size for each VLA type.
121-
// We track this by the size expression rather than the type itself because
122-
// in certain situations, like a const qualifier applied to an VLA typedef,
123-
// multiple VLA types can share the same size expression.
124-
// FIXME: Maybe this could be a stack of maps that is pushed/popped as we
125-
// enter/leave scopes.
126-
llvm::DenseMap<const Expr *, mlir::Value> vlaSizeMap;
127-
128120
public:
129121
/// A non-RAII class containing all the information about a bound
130122
/// opaque value. OpaqueValueMapping, below, is a RAII wrapper for
@@ -364,8 +356,6 @@ class CIRGenFunction : public CIRGenTypeCache {
364356
/// the boolean result in Result.
365357
bool constantFoldsToBool(const clang::Expr *cond, bool &resultBool,
366358
bool allowLabels = false);
367-
bool constantFoldsToSimpleInteger(const clang::Expr *cond, bool &resultBool,
368-
bool allowLabels = false);
369359
bool constantFoldsToSimpleInteger(const clang::Expr *cond,
370360
llvm::APSInt &resultInt,
371361
bool allowLabels = false);

‎clang/test/CIR/CodeGen/binop.cpp

Lines changed: 86 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -575,47 +575,75 @@ void b1(bool a, bool b) {
575575

576576

577577
// LLVM-LABEL: define void @_Z2b1bb(
578-
// LLVM-SAME: i1 %[[ARG0:[0-9]+]], i1 %[[ARG1:[0-9]+]])
579-
// LLVM: %[[A_ADDR:.*]] = alloca i8, i64 1
580-
// LLVM: %[[B_ADDR:.*]] = alloca i8, i64 1
581-
// LLVM: %[[X:.*]] = alloca i8, i64 1
578+
// LLVM-SAME: i1 %[[ARG0:.+]], i1 %[[ARG1:.+]])
579+
// LLVM: %[[A_ADDR:.*]] = alloca i8
580+
// LLVM: %[[B_ADDR:.*]] = alloca i8
581+
// LLVM: %[[X:.*]] = alloca i8
582582
// LLVM: %[[ZEXT0:.*]] = zext i1 %[[ARG0]] to i8
583583
// LLVM: store i8 %[[ZEXT0]], ptr %[[A_ADDR]]
584584
// LLVM: %[[ZEXT1:.*]] = zext i1 %[[ARG1]] to i8
585585
// LLVM: store i8 %[[ZEXT1]], ptr %[[B_ADDR]]
586586
// LLVM: %[[A_VAL:.*]] = load i8, ptr %[[A_ADDR]]
587587
// LLVM: %[[A_BOOL:.*]] = trunc i8 %[[A_VAL]] to i1
588-
// LLVM: br i1 %[[A_BOOL]], label %[[AND_TRUE:[0-9]+]], label %[[AND_FALSE:[0-9]+]]
588+
// LLVM: br i1 %[[A_BOOL]], label %[[AND_TRUE:.+]], label %[[AND_FALSE:.+]]
589589
// LLVM: [[AND_TRUE]]:
590590
// LLVM: %[[B_VAL:.*]] = load i8, ptr %[[B_ADDR]]
591591
// LLVM: %[[B_BOOL:.*]] = trunc i8 %[[B_VAL]] to i1
592-
// LLVM: br label %[[AND_MERGE:[0-9]+]]
592+
// LLVM: br label %[[AND_MERGE:.+]]
593593
// LLVM: [[AND_FALSE]]:
594594
// LLVM: br label %[[AND_MERGE]]
595595
// LLVM: [[AND_MERGE]]:
596596
// LLVM: %[[AND_PHI:.*]] = phi i1 [ false, %[[AND_FALSE]] ], [ %[[B_BOOL]], %[[AND_TRUE]] ]
597-
// LLVM: br label %[[AND_CONT:[0-9]+]]
598-
// LLVM: [[AND_CONT]]:
599597
// LLVM: %[[ZEXT_AND:.*]] = zext i1 %[[AND_PHI]] to i8
600598
// LLVM: store i8 %[[ZEXT_AND]], ptr %[[X]]
601599
// LLVM: %[[X_VAL:.*]] = load i8, ptr %[[X]]
602600
// LLVM: %[[X_BOOL:.*]] = trunc i8 %[[X_VAL]] to i1
603-
// LLVM: br i1 %[[X_BOOL]], label %[[OR_TRUE:[0-9]+]], label %[[OR_FALSE:[0-9]+]]
601+
// LLVM: br i1 %[[X_BOOL]], label %[[OR_TRUE:.+]], label %[[OR_FALSE:.+]]
604602
// LLVM: [[OR_TRUE]]:
605-
// LLVM: br label %[[OR_MERGE:[0-9]+]]
603+
// LLVM: br label %[[OR_MERGE:.+]]
606604
// LLVM: [[OR_FALSE]]:
607605
// LLVM: %[[B_VAL2:.*]] = load i8, ptr %[[B_ADDR]]
608606
// LLVM: %[[B_BOOL2:.*]] = trunc i8 %[[B_VAL2]] to i1
609607
// LLVM: br label %[[OR_MERGE]]
610608
// LLVM: [[OR_MERGE]]:
611609
// LLVM: %[[OR_PHI:.*]] = phi i1 [ %[[B_BOOL2]], %[[OR_FALSE]] ], [ true, %[[OR_TRUE]] ]
612-
// LLVM: br label %[[OR_CONT:[0-9]+]]
613-
// LLVM: [[OR_CONT]]:
614610
// LLVM: %[[ZEXT_OR:.*]] = zext i1 %[[OR_PHI]] to i8
615611
// LLVM: store i8 %[[ZEXT_OR]], ptr %[[X]]
616612
// LLVM: ret void
617613

618-
614+
// OGCG-LABEL: define dso_local void @_Z2b1bb
615+
// OGCG-SAME: (i1 {{.*}} %[[ARG0:.+]], i1 {{.*}} %[[ARG1:.+]])
616+
// OGCG: [[ENTRY:.*]]:
617+
// OGCG: %[[A_ADDR:.*]] = alloca i8
618+
// OGCG: %[[B_ADDR:.*]] = alloca i8
619+
// OGCG: %[[X:.*]] = alloca i8
620+
// OGCG: %[[ZEXT0:.*]] = zext i1 %[[ARG0]] to i8
621+
// OGCG: store i8 %[[ZEXT0]], ptr %[[A_ADDR]]
622+
// OGCG: %[[ZEXT1:.*]] = zext i1 %[[ARG1]] to i8
623+
// OGCG: store i8 %[[ZEXT1]], ptr %[[B_ADDR]]
624+
// OGCG: %[[A_VAL:.*]] = load i8, ptr %[[A_ADDR]]
625+
// OGCG: %[[A_BOOL:.*]] = trunc i8 %[[A_VAL]] to i1
626+
// OGCG: br i1 %[[A_BOOL]], label %[[AND_TRUE:.+]], label %[[AND_MERGE:.+]]
627+
// OGCG: [[AND_TRUE]]:
628+
// OGCG: %[[B_VAL:.*]] = load i8, ptr %[[B_ADDR]]
629+
// OGCG: %[[B_BOOL:.*]] = trunc i8 %[[B_VAL]] to i1
630+
// OGCG: br label %[[AND_MERGE:.+]]
631+
// OGCG: [[AND_MERGE]]:
632+
// OGCG: %[[AND_PHI:.*]] = phi i1 [ false, %[[ENTRY]] ], [ %[[B_BOOL]], %[[AND_TRUE]] ]
633+
// OGCG: %[[ZEXT_AND:.*]] = zext i1 %[[AND_PHI]] to i8
634+
// OGCG: store i8 %[[ZEXT_AND]], ptr %[[X]]
635+
// OGCG: %[[X_VAL:.*]] = load i8, ptr %[[X]]
636+
// OGCG: %[[X_BOOL:.*]] = trunc i8 %[[X_VAL]] to i1
637+
// OGCG: br i1 %[[X_BOOL]], label %[[OR_MERGE:.+]], label %[[OR_FALSE:.+]]
638+
// OGCG: [[OR_FALSE]]:
639+
// OGCG: %[[B_VAL2:.*]] = load i8, ptr %[[B_ADDR]]
640+
// OGCG: %[[B_BOOL2:.*]] = trunc i8 %[[B_VAL2]] to i1
641+
// OGCG: br label %[[OR_MERGE]]
642+
// OGCG: [[OR_MERGE]]:
643+
// OGCG: %[[OR_PHI:.*]] = phi i1 [ true, %[[AND_MERGE]] ], [ %[[B_BOOL2]], %[[OR_FALSE]] ]
644+
// OGCG: %[[ZEXT_OR:.*]] = zext i1 %[[OR_PHI]] to i8
645+
// OGCG: store i8 %[[ZEXT_OR]], ptr %[[X]]
646+
// OGCG: ret void
619647

620648
void b3(int a, int b, int c, int d) {
621649
bool x = (a == b) && (c == d);
@@ -663,7 +691,7 @@ void b3(int a, int b, int c, int d) {
663691

664692

665693
// LLVM-LABEL: define void @_Z2b3iiii(
666-
// LLVM-SAME: i32 %[[ARG0:[0-9]+]], i32 %[[ARG1:[0-9]+]], i32 %[[ARG2:[0-9]+]], i32 %[[ARG3:[0-9]+]])
694+
// LLVM-SAME: i32 %[[ARG0:.+]], i32 %[[ARG1:.+]], i32 %[[ARG2:.+]], i32 %[[ARG3:.+]])
667695
// LLVM: %[[A_ADDR:.*]] = alloca i32, i64 1
668696
// LLVM: %[[B_ADDR:.*]] = alloca i32, i64 1
669697
// LLVM: %[[C_ADDR:.*]] = alloca i32, i64 1
@@ -676,35 +704,71 @@ void b3(int a, int b, int c, int d) {
676704
// LLVM: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]]
677705
// LLVM: %[[B_VAL:.*]] = load i32, ptr %[[B_ADDR]]
678706
// LLVM: %[[CMP1:.*]] = icmp eq i32 %[[A_VAL]], %[[B_VAL]]
679-
// LLVM: br i1 %[[CMP1]], label %[[AND_TRUE:[0-9]+]], label %[[AND_FALSE:[0-9]+]]
707+
// LLVM: br i1 %[[CMP1]], label %[[AND_TRUE:.+]], label %[[AND_FALSE:.+]]
680708
// LLVM: [[AND_TRUE]]:
681709
// LLVM: %[[C_VAL:.*]] = load i32, ptr %[[C_ADDR]]
682710
// LLVM: %[[D_VAL:.*]] = load i32, ptr %[[D_ADDR]]
683711
// LLVM: %[[CMP2:.*]] = icmp eq i32 %[[C_VAL]], %[[D_VAL]]
684-
// LLVM: br label %[[AND_MERGE:[0-9]+]]
712+
// LLVM: br label %[[AND_MERGE:.+]]
685713
// LLVM: [[AND_FALSE]]:
686714
// LLVM: br label %[[AND_MERGE]]
687715
// LLVM: [[AND_MERGE]]:
688716
// LLVM: %[[AND_PHI:.*]] = phi i1 [ false, %[[AND_FALSE]] ], [ %[[CMP2]], %[[AND_TRUE]] ]
689-
// LLVM: br label %[[AND_CONT:[0-9]+]]
690-
// LLVM: [[AND_CONT]]:
691717
// LLVM: %[[ZEXT_AND:.*]] = zext i1 %[[AND_PHI]] to i8
692718
// LLVM: store i8 %[[ZEXT_AND]], ptr %[[X]]
693719
// LLVM: %[[A_VAL2:.*]] = load i32, ptr %[[A_ADDR]]
694720
// LLVM: %[[B_VAL2:.*]] = load i32, ptr %[[B_ADDR]]
695721
// LLVM: %[[CMP3:.*]] = icmp eq i32 %[[A_VAL2]], %[[B_VAL2]]
696-
// LLVM: br i1 %[[CMP3]], label %[[OR_TRUE:[0-9]+]], label %[[OR_FALSE:[0-9]+]]
722+
// LLVM: br i1 %[[CMP3]], label %[[OR_TRUE:.+]], label %[[OR_FALSE:.+]]
697723
// LLVM: [[OR_TRUE]]:
698-
// LLVM: br label %[[OR_MERGE:[0-9]+]]
724+
// LLVM: br label %[[OR_MERGE:.+]]
699725
// LLVM: [[OR_FALSE]]:
700726
// LLVM: %[[C_VAL2:.*]] = load i32, ptr %[[C_ADDR]]
701727
// LLVM: %[[D_VAL2:.*]] = load i32, ptr %[[D_ADDR]]
702728
// LLVM: %[[CMP4:.*]] = icmp eq i32 %[[C_VAL2]], %[[D_VAL2]]
703729
// LLVM: br label %[[OR_MERGE]]
704730
// LLVM: [[OR_MERGE]]:
705731
// LLVM: %[[OR_PHI:.*]] = phi i1 [ %[[CMP4]], %[[OR_FALSE]] ], [ true, %[[OR_TRUE]] ]
706-
// LLVM: br label %[[OR_CONT:[0-9]+]]
707-
// LLVM: [[OR_CONT]]:
708732
// LLVM: %[[ZEXT_OR:.*]] = zext i1 %[[OR_PHI]] to i8
709733
// LLVM: store i8 %[[ZEXT_OR]], ptr %[[X]]
710734
// LLVM: ret void
735+
736+
// OGCG-LABEL: define dso_local void @_Z2b3iiii(
737+
// OGCG-SAME: i32 {{.*}} %[[ARG0:.+]], i32 {{.*}} %[[ARG1:.+]], i32 {{.*}} %[[ARG2:.+]], i32 {{.*}} %[[ARG3:.+]])
738+
// OGCG: [[ENTRY:.*]]:
739+
// OGCG: %[[A_ADDR:.*]] = alloca i32
740+
// OGCG: %[[B_ADDR:.*]] = alloca i32
741+
// OGCG: %[[C_ADDR:.*]] = alloca i32
742+
// OGCG: %[[D_ADDR:.*]] = alloca i32
743+
// OGCG: %[[X:.*]] = alloca i8
744+
// OGCG: store i32 %[[ARG0]], ptr %[[A_ADDR]]
745+
// OGCG: store i32 %[[ARG1]], ptr %[[B_ADDR]]
746+
// OGCG: store i32 %[[ARG2]], ptr %[[C_ADDR]]
747+
// OGCG: store i32 %[[ARG3]], ptr %[[D_ADDR]]
748+
// OGCG: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]]
749+
// OGCG: %[[B_VAL:.*]] = load i32, ptr %[[B_ADDR]]
750+
// OGCG: %[[CMP1:.*]] = icmp eq i32 %[[A_VAL]], %[[B_VAL]]
751+
// OGCG: br i1 %[[CMP1]], label %[[AND_TRUE:.+]], label %[[AND_MERGE:.+]]
752+
// OGCG: [[AND_TRUE]]:
753+
// OGCG: %[[C_VAL:.*]] = load i32, ptr %[[C_ADDR]]
754+
// OGCG: %[[D_VAL:.*]] = load i32, ptr %[[D_ADDR]]
755+
// OGCG: %[[CMP2:.*]] = icmp eq i32 %[[C_VAL]], %[[D_VAL]]
756+
// OGCG: br label %[[AND_MERGE:.+]]
757+
// OGCG: [[AND_MERGE]]:
758+
// OGCG: %[[AND_PHI:.*]] = phi i1 [ false, %[[ENTRY]] ], [ %[[CMP2]], %[[AND_TRUE]] ]
759+
// OGCG: %[[ZEXT_AND:.*]] = zext i1 %[[AND_PHI]] to i8
760+
// OGCG: store i8 %[[ZEXT_AND]], ptr %[[X]]
761+
// OGCG: %[[A_VAL2:.*]] = load i32, ptr %[[A_ADDR]]
762+
// OGCG: %[[B_VAL2:.*]] = load i32, ptr %[[B_ADDR]]
763+
// OGCG: %[[CMP3:.*]] = icmp eq i32 %[[A_VAL2]], %[[B_VAL2]]
764+
// OGCG: br i1 %[[CMP3]], label %[[OR_MERGE:.+]], label %[[OR_FALSE:.+]]
765+
// OGCG: [[OR_FALSE]]:
766+
// OGCG: %[[C_VAL2:.*]] = load i32, ptr %[[C_ADDR]]
767+
// OGCG: %[[D_VAL2:.*]] = load i32, ptr %[[D_ADDR]]
768+
// OGCG: %[[CMP4:.*]] = icmp eq i32 %[[C_VAL2]], %[[D_VAL2]]
769+
// OGCG: br label %[[OR_MERGE]]
770+
// OGCG: [[OR_MERGE]]:
771+
// OGCG: %[[OR_PHI:.*]] = phi i1 [ true, %[[AND_MERGE]] ], [ %[[CMP4]], %[[OR_FALSE]] ]
772+
// OGCG: %[[ZEXT_OR:.*]] = zext i1 %[[OR_PHI]] to i8
773+
// OGCG: store i8 %[[ZEXT_OR]], ptr %[[X]]
774+
// OGCG: ret void

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