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[AMDGPU] Create AMDGPUMnemonicAlias tablegen class
AMDGPUMnemonicAlias is a MnemonicAlias that inherits from GCNPredicateControl, so that we can set predicates on the alias the same way as Instructions. Use AssemblerPredicate instead of Requires in aliases NFC.
1 parent 44713f1 commit 6ff20ce

14 files changed

+137
-78
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPU.td

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1909,7 +1909,8 @@ def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
19091909

19101910
def HasTrue16BitInsts : Predicate<"Subtarget->hasTrue16BitInsts()">,
19111911
AssemblerPredicate<(all_of FeatureTrue16BitInsts)>;
1912-
def NotHasTrue16BitInsts : True16PredicateClass<"!Subtarget->hasTrue16BitInsts()">;
1912+
def NotHasTrue16BitInsts : True16PredicateClass<"!Subtarget->hasTrue16BitInsts()">,
1913+
AssemblerPredicate<(all_of (not FeatureTrue16BitInsts))>;
19131914

19141915
// Control use of True16 instructions. The real True16 instructions are
19151916
// True16 instructions as they are defined in the ISA. Fake True16
@@ -1918,7 +1919,10 @@ def NotHasTrue16BitInsts : True16PredicateClass<"!Subtarget->hasTrue16BitInsts()
19181919
def UseRealTrue16Insts : True16PredicateClass<"Subtarget->useRealTrue16Insts()">,
19191920
AssemblerPredicate<(all_of FeatureTrue16BitInsts, FeatureRealTrue16Insts)>;
19201921
def UseFakeTrue16Insts : True16PredicateClass<"Subtarget->hasTrue16BitInsts() && "
1921-
"!Subtarget->useRealTrue16Insts()">;
1922+
"!Subtarget->useRealTrue16Insts()">,
1923+
AssemblerPredicate<(all_of FeatureTrue16BitInsts)>;
1924+
// FIXME When we default to RealTrue16 instead of Fake, change the line as follows.
1925+
// AssemblerPredicate<(all_of FeatureTrue16BitInsts, (not FeatureRealTrue16Insts))>;
19221926

19231927
def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
19241928
AssemblerPredicate<(all_of FeatureVOP3P)>;

‎llvm/lib/Target/AMDGPU/BUFInstructions.td

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2456,13 +2456,19 @@ class get_BUF_ps<string name> {
24562456

24572457
// gfx11 instruction that accept both old and new assembler name.
24582458
class Mnem_gfx11_gfx12 <string mnemonic, string real_name> :
2459-
MnemonicAlias<mnemonic, real_name>, Requires<[isGFX11Plus]>;
2459+
AMDGPUMnemonicAlias<mnemonic, real_name> {
2460+
let AssemblerPredicate = isGFX11Plus;
2461+
}
24602462

24612463
class Mnem_gfx11 <string mnemonic, string real_name> :
2462-
MnemonicAlias<mnemonic, real_name>, Requires<[isGFX11Only]>;
2464+
AMDGPUMnemonicAlias<mnemonic, real_name> {
2465+
let AssemblerPredicate = isGFX11Only;
2466+
}
24632467

24642468
class Mnem_gfx12 <string mnemonic, string real_name> :
2465-
MnemonicAlias<mnemonic, real_name>, Requires<[isGFX12Plus]>;
2469+
AMDGPUMnemonicAlias<mnemonic, real_name> {
2470+
let AssemblerPredicate = isGFX12Plus;
2471+
}
24662472

24672473
multiclass MUBUF_Real_AllAddr_gfx11_Impl2<bits<8> op, string real_name> {
24682474
defm _BOTHEN : MUBUF_Real_gfx11<op, real_name>;

‎llvm/lib/Target/AMDGPU/DSInstructions.td

Lines changed: 20 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1213,12 +1213,14 @@ class Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<bits<8> op, DS_Pseudo ps, int ef,
12131213

12141214
multiclass DS_Real_gfx12<bits<8> op, string name = !tolower(NAME), bit needAlias = true> {
12151215
defvar ps = !cast<DS_Pseudo>(NAME);
1216-
let AssemblerPredicate = isGFX12Plus, DecoderNamespace = "GFX12" in
1217-
def _gfx12 :
1218-
Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<op, ps, SIEncodingFamily.GFX12,
1216+
let AssemblerPredicate = isGFX12Plus in {
1217+
let DecoderNamespace = "GFX12" in
1218+
def _gfx12 :
1219+
Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<op, ps, SIEncodingFamily.GFX12,
12191220
name, /*hasGDS=*/false>;
1220-
if !and(needAlias, !ne(ps.Mnemonic, name)) then
1221-
def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX12Plus]>;
1221+
if !and(needAlias, !ne(ps.Mnemonic, name)) then
1222+
def : AMDGPUMnemonicAlias<ps.Mnemonic, name>;
1223+
} // End AssemblerPredicate
12221224
}
12231225

12241226
defm DS_MIN_F32 : DS_Real_gfx12<0x012, "ds_min_num_f32">;
@@ -1239,23 +1241,27 @@ defm DS_PK_ADD_BF16 : DS_Real_gfx12<0x09b>;
12391241
defm DS_PK_ADD_RTN_BF16 : DS_Real_gfx12<0x0ab>;
12401242

12411243
// New aliases added in GFX12 without renaming the instructions.
1242-
def : MnemonicAlias<"ds_subrev_u32", "ds_rsub_u32">, Requires<[isGFX12Plus]>;
1243-
def : MnemonicAlias<"ds_subrev_rtn_u32", "ds_rsub_rtn_u32">, Requires<[isGFX12Plus]>;
1244-
def : MnemonicAlias<"ds_subrev_u64", "ds_rsub_u64">, Requires<[isGFX12Plus]>;
1245-
def : MnemonicAlias<"ds_subrev_rtn_u64", "ds_rsub_rtn_u64">, Requires<[isGFX12Plus]>;
1244+
let AssemblerPredicate = isGFX12Plus in {
1245+
def : AMDGPUMnemonicAlias<"ds_subrev_u32", "ds_rsub_u32">;
1246+
def : AMDGPUMnemonicAlias<"ds_subrev_rtn_u32", "ds_rsub_rtn_u32">;
1247+
def : AMDGPUMnemonicAlias<"ds_subrev_u64", "ds_rsub_u64">;
1248+
def : AMDGPUMnemonicAlias<"ds_subrev_rtn_u64", "ds_rsub_rtn_u64">;
1249+
}
12461250

12471251
//===----------------------------------------------------------------------===//
12481252
// GFX11.
12491253
//===----------------------------------------------------------------------===//
12501254

12511255
multiclass DS_Real_gfx11<bits<8> op, string name = !tolower(NAME)> {
12521256
defvar ps = !cast<DS_Pseudo>(NAME);
1253-
let AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11" in
1254-
def _gfx11 :
1255-
Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<op, ps, SIEncodingFamily.GFX11,
1257+
let AssemblerPredicate = isGFX11Only in {
1258+
let DecoderNamespace = "GFX11" in
1259+
def _gfx11 :
1260+
Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<op, ps, SIEncodingFamily.GFX11,
12561261
name>;
1257-
if !ne(ps.Mnemonic, name) then
1258-
def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX11Only]>;
1262+
if !ne(ps.Mnemonic, name) then
1263+
def : AMDGPUMnemonicAlias<ps.Mnemonic, name>;
1264+
} // End AssemblerPredicate
12591265
}
12601266

12611267
multiclass DS_Real_gfx11_gfx12<bits<8> op, string name = !tolower(NAME)>

‎llvm/lib/Target/AMDGPU/EXPInstructions.td

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -117,12 +117,16 @@ multiclass EXP_Real_gfx11 {
117117
multiclass VEXPORT_Real_gfx12 {
118118
defvar ps = !cast<EXP_Pseudo>(NAME);
119119
def _gfx12 : EXP_Real_Row<ps, SIEncodingFamily.GFX12, "export">,
120-
EXPe_Row, MnemonicAlias<"exp", "export">, Requires<[isGFX12Plus, HasExportInsts]> {
120+
EXPe_Row {
121121
let AssemblerPredicate = isGFX12Only;
122122
let DecoderNamespace = "GFX12";
123123
let row = ps.row;
124124
let done = ps.done;
125125
}
126+
def : AMDGPUMnemonicAlias<"exp", "export"> {
127+
let AssemblerPredicate = isGFX12Plus;
128+
let OtherPredicates = [HasExportInsts];
129+
}
126130
}
127131

128132
defm EXP : EXP_Real_gfx11, VEXPORT_Real_gfx12;

‎llvm/lib/Target/AMDGPU/FLATInstructions.td

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2357,7 +2357,9 @@ multiclass FLAT_Real_gfx11 <bits<7> op,
23572357
multiclass FLAT_Aliases_gfx11<string name> {
23582358
defvar ps = get_FLAT_ps<NAME>;
23592359
if !ne(ps.Mnemonic, name) then
2360-
def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX11Only]>;
2360+
def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
2361+
let AssemblerPredicate = isGFX11Only;
2362+
}
23612363
}
23622364

23632365
multiclass FLAT_Real_Base_gfx11<bits<7> op,
@@ -2544,10 +2546,12 @@ multiclass VFLAT_Real_gfx12 <bits<8> op, string name = get_FLAT_ps<NAME>.Mnemoni
25442546

25452547
multiclass VFLAT_Aliases_gfx12<string name, string alias = name> {
25462548
defvar ps = get_FLAT_ps<NAME>;
2547-
if !ne(ps.Mnemonic, name) then
2548-
def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX12Only]>;
2549-
if !ne(alias, name) then
2550-
def : MnemonicAlias<alias, name>, Requires<[isGFX12Only]>;
2549+
let AssemblerPredicate = isGFX12Only in {
2550+
if !ne(ps.Mnemonic, name) then
2551+
def : AMDGPUMnemonicAlias<ps.Mnemonic, name>;
2552+
if !ne(alias, name) then
2553+
def : AMDGPUMnemonicAlias<alias, name>;
2554+
}
25512555
}
25522556

25532557
multiclass VFLAT_Real_Base_gfx12<bits<8> op,

‎llvm/lib/Target/AMDGPU/MIMGInstructions.td

Lines changed: 14 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -963,11 +963,10 @@ class VIMAGE_Atomic_gfx12<mimgopc op, string opcode, RegisterClass DataRC,
963963
let AsmString = opcode#" $vdata, "#AddrAsm#", $rsrc$dmask$dim$cpol$r128$a16$tfe";
964964
}
965965

966-
class VIMAGE_Atomic_gfx12_Renamed<mimgopc op, string opcode, string renamed,
966+
class VIMAGE_Atomic_gfx12_Renamed<mimgopc op, string renamed,
967967
RegisterClass DataRC, int num_addrs,
968968
bit enableDisasm = 0>
969-
: VIMAGE_Atomic_gfx12<op, renamed, DataRC, num_addrs, enableDisasm>,
970-
MnemonicAlias<opcode, renamed>, Requires<[isGFX12Plus, HasImageInsts]>;
969+
: VIMAGE_Atomic_gfx12<op, renamed, DataRC, num_addrs, enableDisasm>;
971970

972971
multiclass MIMG_Atomic_Addr_Helper_m <mimgopc op, string asm,
973972
RegisterClass data_rc,
@@ -998,7 +997,7 @@ multiclass MIMG_Atomic_Addr_Helper_m <mimgopc op, string asm,
998997
if !empty(renamed) then
999998
def _V1_gfx12 : VIMAGE_Atomic_gfx12 <op, asm, data_rc, 1, enableDasm>;
1000999
else
1001-
def _V1_gfx12 : VIMAGE_Atomic_gfx12_Renamed <op, asm, renamed, data_rc, 1, enableDasm>;
1000+
def _V1_gfx12 : VIMAGE_Atomic_gfx12_Renamed <op, renamed, data_rc, 1, enableDasm>;
10021001
}
10031002
}
10041003
let VAddrDwords = 2 in {
@@ -1023,7 +1022,7 @@ multiclass MIMG_Atomic_Addr_Helper_m <mimgopc op, string asm,
10231022
if !empty(renamed) then
10241023
def _V2_gfx12 : VIMAGE_Atomic_gfx12 <op, asm, data_rc, 2, 0>;
10251024
else
1026-
def _V2_gfx12 : VIMAGE_Atomic_gfx12_Renamed <op, asm, renamed, data_rc, 2, 0>;
1025+
def _V2_gfx12 : VIMAGE_Atomic_gfx12_Renamed <op, renamed, data_rc, 2, 0>;
10271026
}
10281027
}
10291028
let VAddrDwords = 3 in {
@@ -1048,7 +1047,7 @@ multiclass MIMG_Atomic_Addr_Helper_m <mimgopc op, string asm,
10481047
if !empty(renamed) then
10491048
def _V3_gfx12 : VIMAGE_Atomic_gfx12 <op, asm, data_rc, 3, 0>;
10501049
else
1051-
def _V3_gfx12 : VIMAGE_Atomic_gfx12_Renamed <op, asm, renamed, data_rc, 3, 0>;
1050+
def _V3_gfx12 : VIMAGE_Atomic_gfx12_Renamed <op, renamed, data_rc, 3, 0>;
10521051
}
10531052
}
10541053
let VAddrDwords = 4 in {
@@ -1073,10 +1072,18 @@ multiclass MIMG_Atomic_Addr_Helper_m <mimgopc op, string asm,
10731072
if !empty(renamed) then
10741073
def _V4_gfx12 : VIMAGE_Atomic_gfx12 <op, asm, data_rc, 4, enableDasm>;
10751074
else
1076-
def _V4_gfx12 : VIMAGE_Atomic_gfx12_Renamed <op, asm, renamed, data_rc, 4, enableDasm>;
1075+
def _V4_gfx12 : VIMAGE_Atomic_gfx12_Renamed <op, renamed, data_rc, 4, enableDasm>;
10771076
}
10781077
}
10791078
}
1079+
if !and(op.HAS_GFX12, !not(!empty(renamed))) then
1080+
def : AMDGPUMnemonicAlias<asm, renamed> {
1081+
let AssemblerPredicate = isGFX12Plus;
1082+
let OtherPredicates = [HasImageInsts];
1083+
bit IsAtomicRet; // Unused
1084+
MIMGBaseOpcode BaseOpcode; // Unused
1085+
int VDataDwords; // Unused
1086+
}
10801087
}
10811088

10821089
multiclass MIMG_Atomic <mimgopc op, string asm, bit isCmpSwap = 0, bit isFP = 0,

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,9 @@ class GCNPredicateControl : PredicateControl {
1616
Predicate VIAssemblerPredicate = isGFX8GFX9;
1717
}
1818

19+
class AMDGPUMnemonicAlias<string From, string To, string VariantName = "">
20+
: MnemonicAlias<From, To, VariantName>, GCNPredicateControl;
21+
1922
// Except for the NONE field, this must be kept in sync with the
2023
// SIEncodingFamily enum in SIInstrInfo.cpp and the columns of the
2124
// getMCOpcodeGen table.

‎llvm/lib/Target/AMDGPU/SMInstructions.td

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1332,8 +1332,9 @@ multiclass SM_Real_Loads_gfx11<bits<8> op, string ps> {
13321332
def _IMM_gfx11 : SMEM_Real_Load_gfx11<op, ps#"_IMM", opName>;
13331333
def _SGPR_gfx11 : SMEM_Real_Load_gfx11<op, ps#"_SGPR", opName>;
13341334
def _SGPR_IMM_gfx11 : SMEM_Real_Load_gfx11<op, ps#"_SGPR_IMM", opName>;
1335-
def : MnemonicAlias<!cast<SM_Pseudo>(ps#"_IMM").Mnemonic, opName>,
1336-
Requires<[isGFX11Plus]>;
1335+
def : AMDGPUMnemonicAlias<!cast<SM_Pseudo>(ps#"_IMM").Mnemonic, opName> {
1336+
let AssemblerPredicate = isGFX11Plus;
1337+
}
13371338
}
13381339

13391340
defm S_LOAD_B32 : SM_Real_Loads_gfx11<0x000, "S_LOAD_DWORD">;

‎llvm/lib/Target/AMDGPU/SOPInstructions.td

Lines changed: 21 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1974,15 +1974,19 @@ multiclass SOP1_Real_gfx11<bits<8> op, string name = !tolower(NAME)> {
19741974
def _gfx11 : SOP1_Real<op, ps, name>,
19751975
Select_gfx11<ps.PseudoInstr>;
19761976
if !ne(ps.Mnemonic, name) then
1977-
def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX11Only]>;
1977+
def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
1978+
let AssemblerPredicate = isGFX11Only;
1979+
}
19781980
}
19791981

19801982
multiclass SOP1_Real_gfx12<bits<8> op, string name = !tolower(NAME)> {
19811983
defvar ps = !cast<SOP1_Pseudo>(NAME);
19821984
def _gfx12 : SOP1_Real<op, ps, name>,
19831985
Select_gfx12<ps.PseudoInstr>;
19841986
if !ne(ps.Mnemonic, name) then
1985-
def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX12Plus]>;
1987+
def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
1988+
let AssemblerPredicate = isGFX12Plus;
1989+
}
19861990
}
19871991

19881992
multiclass SOP1_M0_Real_gfx12<bits<8> op> {
@@ -2207,7 +2211,9 @@ multiclass SOP2_Real_gfx12<bits<7> op, string name = !tolower(NAME)> {
22072211
def _gfx12 : SOP2_Real32<op, ps, name>,
22082212
Select_gfx12<ps.PseudoInstr>;
22092213
if !ne(ps.Mnemonic, name) then
2210-
def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX12Plus]>;
2214+
def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
2215+
let AssemblerPredicate = isGFX12Plus;
2216+
}
22112217
}
22122218

22132219
defm S_MINIMUM_F32 : SOP2_Real_gfx12<0x04f>;
@@ -2224,7 +2230,9 @@ multiclass SOP2_Real_gfx11<bits<7> op, string name = !tolower(NAME)> {
22242230
def _gfx11 : SOP2_Real32<op, ps, name>,
22252231
Select_gfx11<ps.PseudoInstr>;
22262232
if !ne(ps.Mnemonic, name) then
2227-
def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX11Only]>;
2233+
def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
2234+
let AssemblerPredicate = isGFX11Only;
2235+
}
22282236
}
22292237

22302238
multiclass SOP2_Real_gfx11_gfx12<bits<7> op, string name = !tolower(NAME)> :
@@ -2412,7 +2420,9 @@ multiclass SOPK_Real32_gfx12<bits<5> op, string name = !tolower(NAME)> {
24122420
def _gfx12 : SOPK_Real32<op, ps, name>,
24132421
Select_gfx12<ps.PseudoInstr>;
24142422
if !ne(ps.Mnemonic, name) then
2415-
def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX12Plus]>;
2423+
def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
2424+
let AssemblerPredicate = isGFX12Plus;
2425+
}
24162426
}
24172427

24182428
multiclass SOPK_Real32_gfx11<bits<5> op> {
@@ -2541,7 +2551,9 @@ multiclass SOPP_Real_32_gfx12<bits<7> op, string name = !tolower(NAME)> {
25412551
def _gfx12 : SOPP_Real_32<op, ps, name>,
25422552
Select_gfx12<ps.PseudoInstr>;
25432553
if !ne(ps.Mnemonic, name) then
2544-
def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX12Plus]>;
2554+
def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
2555+
let AssemblerPredicate = isGFX12Plus;
2556+
}
25452557
}
25462558

25472559
defm S_BARRIER_WAIT : SOPP_Real_32_gfx12<0x014>;
@@ -2567,7 +2579,9 @@ multiclass SOPP_Real_32_gfx11<bits<7> op, string name = !tolower(NAME)> {
25672579
Select_gfx11<ps.PseudoInstr>,
25682580
SOPPRelaxTable<0, ps.KeyName, "_gfx11">;
25692581
if !ne(ps.Mnemonic, name) then
2570-
def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX11Only]>;
2582+
def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
2583+
let AssemblerPredicate = isGFX11Only;
2584+
}
25712585
}
25722586

25732587
multiclass SOPP_Real_64_gfx12<bits<7> op> {

‎llvm/lib/Target/AMDGPU/VOP1Instructions.td

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -143,14 +143,14 @@ multiclass VOP1Inst <string opName, VOPProfile P,
143143
def _e64_dpp : VOP3_DPP_Pseudo <opName, P>;
144144
} // End SubtargetPredicate = isGFX11Plus
145145

146-
def : MnemonicAlias<opName#"_e32", opName>, LetDummies;
147-
def : MnemonicAlias<opName#"_e64", opName>, LetDummies;
146+
def : LetDummies, AMDGPUMnemonicAlias<opName#"_e32", opName>;
147+
def : LetDummies, AMDGPUMnemonicAlias<opName#"_e64", opName>;
148148

149149
if P.HasExtSDWA then
150-
def : MnemonicAlias<opName#"_sdwa", opName>, LetDummies;
150+
def : LetDummies, AMDGPUMnemonicAlias<opName#"_sdwa", opName>;
151151

152152
if P.HasExtDPP then
153-
def : MnemonicAlias<opName#"_dpp", opName, AMDGPUAsmVariants.DPP>, LetDummies;
153+
def : LetDummies, AMDGPUMnemonicAlias<opName#"_dpp", opName, AMDGPUAsmVariants.DPP>;
154154
}
155155

156156
multiclass VOP1Inst_t16<string opName,
@@ -858,8 +858,9 @@ multiclass VOP1_Real_NO_VOP3_with_name_gfx11<bits<9> op, string opName,
858858
VOP1_Real_dpp_with_name<GFX11Gen, op, opName, asmName>,
859859
VOP1_Real_dpp8_with_name<GFX11Gen, op, opName, asmName>;
860860
defvar ps = !cast<VOP1_Pseudo>(opName#"_e32");
861-
def gfx11_alias : MnemonicAlias<ps.Mnemonic, asmName>,
862-
Requires<[isGFX11Plus]>;
861+
def gfx11_alias : AMDGPUMnemonicAlias<ps.Mnemonic, asmName> {
862+
let AssemblerPredicate = isGFX11Plus;
863+
}
863864
}
864865

865866
multiclass VOP1_Real_NO_VOP3_with_name_gfx12<bits<9> op, string opName,

‎llvm/lib/Target/AMDGPU/VOP2Instructions.td

Lines changed: 15 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1510,7 +1510,9 @@ multiclass VOP2_Real_NO_VOP3_with_name<GFXGen Gen, bits<6> op, string opName,
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VOP2_Real_dpp_with_name<Gen, op, opName, asmName>,
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VOP2_Real_dpp8_with_name<Gen, op, opName, asmName>;
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defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");
1513-
def Gen.Suffix#"_alias" : MnemonicAlias<ps.Mnemonic, asmName>, Requires<[Gen.AssemblerPredicate]>;
1513+
def Gen.Suffix#"_alias" : AMDGPUMnemonicAlias<ps.Mnemonic, asmName> {
1514+
let AssemblerPredicate = Gen.AssemblerPredicate;
1515+
}
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}
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multiclass VOP2_Real_FULL_with_name<GFXGen Gen, bits<6> op, string opName,
@@ -1523,13 +1525,17 @@ multiclass VOP2_Real_NO_DPP_with_name<GFXGen Gen, bits<6> op, string opName,
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defm NAME : VOP2_Real_e32_with_name<Gen, op, opName, asmName>,
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VOP2_Real_e64_with_name<Gen, op, opName, asmName>;
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defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");
1526-
def Gen.Suffix#"_alias" : MnemonicAlias<ps.Mnemonic, asmName>, Requires<[Gen.AssemblerPredicate]>;
1528+
def Gen.Suffix#"_alias" : AMDGPUMnemonicAlias<ps.Mnemonic, asmName> {
1529+
let AssemblerPredicate = Gen.AssemblerPredicate;
1530+
}
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}
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multiclass VOP2_Real_NO_DPP_with_alias<GFXGen Gen, bits<6> op, string alias> {
15301534
defm NAME : VOP2_Real_e32<Gen, op>,
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VOP2_Real_e64<Gen, op>;
1532-
def Gen.Suffix#"_alias" : MnemonicAlias<alias, NAME>, Requires<[Gen.AssemblerPredicate]>;
1536+
def Gen.Suffix#"_alias" : AMDGPUMnemonicAlias<alias, NAME> {
1537+
let AssemblerPredicate = Gen.AssemblerPredicate;
1538+
}
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}
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15351541
//===----------------------------------------------------------------------===//
@@ -1550,7 +1556,9 @@ multiclass VOP2_Real_FULL_with_name_gfx12<bits<6> op, string opName,
15501556
multiclass VOP2_Real_FULL_t16_with_name_gfx12<bits<6> op, string opName,
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string asmName, string alias> {
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defm NAME : VOP2_Real_FULL_with_name<GFX12Gen, op, opName, asmName>;
1553-
def _gfx12_2nd_alias : MnemonicAlias<alias, asmName>, Requires<[isGFX12Only]>;
1559+
def _gfx12_2nd_alias : AMDGPUMnemonicAlias<alias, asmName> {
1560+
let AssemblerPredicate = isGFX12Only;
1561+
}
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}
15551563

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multiclass VOP2_Real_NO_DPP_with_name_gfx12<bits<6> op, string opName,
@@ -1609,7 +1617,9 @@ multiclass VOP2_Real_NO_VOP3_with_name_gfx11<bits<6> op, string opName,
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VOP2_Real_dpp_with_name<GFX11Gen, op, opName, asmName>,
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VOP2_Real_dpp8_with_name<GFX11Gen, op, opName, asmName>;
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defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");
1612-
def _gfx11_alias : MnemonicAlias<ps.Mnemonic, asmName>, Requires<[isGFX11Only]>;
1620+
def _gfx11_alias : AMDGPUMnemonicAlias<ps.Mnemonic, asmName> {
1621+
let AssemblerPredicate = isGFX11Only;
1622+
}
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}
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16151625
multiclass VOP2_Real_NO_DPP_with_name_gfx11<bits<6> op, string opName,

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