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arsenmarsenm
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GlobalISel: Drop vector range metadata on bitcast lowering (#97279)
If we are reinterpreting the type, the range metadata also needs to be converted. I believe the DAG has the same bug.
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‎llvm/include/llvm/CodeGen/MachineMemOperand.h

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@@ -331,6 +331,9 @@ class MachineMemOperand {
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MemoryType = NewTy;
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}
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/// Unset the tracked range metadata.
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void clearRanges() { Ranges = nullptr; }
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/// Support for operator<<.
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/// @{
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void print(raw_ostream &OS, ModuleSlotTracker &MST,

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

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@@ -3639,6 +3639,9 @@ LegalizerHelper::bitcast(MachineInstr &MI, unsigned TypeIdx, LLT CastTy) {
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Observer.changingInstr(MI);
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bitcastDst(MI, CastTy, 0);
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MMO.setType(CastTy);
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// The range metadata is no longer valid when reinterpreted as a different
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// type.
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MMO.clearRanges();
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Observer.changedInstr(MI);
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return Legalized;
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}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/load-legalize-range-metadata.ll

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@@ -0,0 +1,150 @@
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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -stop-after=legalizer -o - %s | FileCheck %s
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; Test behavior of legalizer when vector loads have range metadata,
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; and are lowered by bitcasting to a scalar integer, so we have to
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; drop the range metadata.
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define <4 x i8> @global_load_v4i8_align4__rangemd(ptr addrspace(1) %ptr) {
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; CHECK-LABEL: name: global_load_v4i8_align4__rangemd
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: liveins: $vgpr0, $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p1) :: (load (s32) from %ir.ptr, addrspace 1)
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
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; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C]](s32)
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
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; CHECK-NEXT: $vgpr0 = COPY [[LOAD]](s32)
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; CHECK-NEXT: $vgpr1 = COPY [[LSHR]](s32)
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; CHECK-NEXT: $vgpr2 = COPY [[LSHR1]](s32)
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; CHECK-NEXT: $vgpr3 = COPY [[LSHR2]](s32)
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; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
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%load = load <4 x i8>, ptr addrspace(1) %ptr, align 4, !range !0, !noundef !1
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ret <4 x i8> %load
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}
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; This is also widened.
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define <3 x i8> @global_load_v3i8_align4__rangemd(ptr addrspace(1) %ptr) {
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; CHECK-LABEL: name: global_load_v3i8_align4__rangemd
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: liveins: $vgpr0, $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p1) :: (load (s32) from %ir.ptr, addrspace 1)
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
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; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C]](s32)
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
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; CHECK-NEXT: $vgpr0 = COPY [[LOAD]](s32)
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; CHECK-NEXT: $vgpr1 = COPY [[LSHR]](s32)
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; CHECK-NEXT: $vgpr2 = COPY [[LSHR1]](s32)
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; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
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%load = load <3 x i8>, ptr addrspace(1) %ptr, align 4, !range !0, !noundef !1
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ret <3 x i8> %load
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}
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define <2 x i8> @global_load_v2i8_align2__rangemd(ptr addrspace(1) %ptr) {
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; CHECK-LABEL: name: global_load_v2i8_align2__rangemd
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: liveins: $vgpr0, $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p1) :: (load (s16) from %ir.ptr, addrspace 1)
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
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; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C]](s32)
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; CHECK-NEXT: $vgpr0 = COPY [[LOAD]](s32)
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; CHECK-NEXT: $vgpr1 = COPY [[LSHR]](s32)
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; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
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%load = load <2 x i8>, ptr addrspace(1) %ptr, align 2, !range !0, !noundef !1
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ret <2 x i8> %load
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}
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define <2 x i64> @global_load_v2i64_align16__rangemd(ptr addrspace(1) %ptr) {
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; CHECK-LABEL: name: global_load_v2i64_align16__rangemd
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: liveins: $vgpr0, $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[MV]](p1) :: (load (<2 x s64>) from %ir.ptr, !range !2, addrspace 1)
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; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s64>)
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; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)
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; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)
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; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)
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; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32)
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; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
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%load = load <2 x i64>, ptr addrspace(1) %ptr, align 16, !range !2, !noundef !1
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ret <2 x i64> %load
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}
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; This goes the other direction and converts a scalar load to a vector.
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define i128 @global_load_i128_align16__rangemd(ptr addrspace(1) %ptr) {
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; CHECK-LABEL: name: global_load_i128_align16__rangemd
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: liveins: $vgpr0, $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[MV]](p1) :: (load (<4 x s32>) from %ir.ptr, addrspace 1)
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; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
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; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s128)
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; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)
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; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)
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; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)
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; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32)
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; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
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%load = load i128, ptr addrspace(1) %ptr, align 16, !range !3, !noundef !1
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ret i128 %load
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}
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; Load will be zero extended, so we should be able to extend the range
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; metadata.
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define i32 @global_sextload_i8_align1__rangemd(ptr addrspace(1) %ptr) {
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; CHECK-LABEL: name: global_sextload_i8_align1__rangemd
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: liveins: $vgpr0, $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
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; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[MV]](p1) :: (load (s8) from %ir.ptr, !range !0, addrspace 1)
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; CHECK-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
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; CHECK-NEXT: SI_RETURN implicit $vgpr0
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%load = load i8, ptr addrspace(1) %ptr, align 1, !range !0, !noundef !1
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%ext = sext i8 %load to i32
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ret i32 %ext
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}
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define i32 @global_zextload_i8_align1__rangemd(ptr addrspace(1) %ptr) {
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; CHECK-LABEL: name: global_zextload_i8_align1__rangemd
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: liveins: $vgpr0, $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
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; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[MV]](p1) :: (load (s8) from %ir.ptr, !range !4, addrspace 1)
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; CHECK-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
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; CHECK-NEXT: SI_RETURN implicit $vgpr0
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%load = load i8, ptr addrspace(1) %ptr, align 1, !range !4, !noundef !1
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%ext = sext i8 %load to i32
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ret i32 %ext
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}
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!0 = !{i8 -32, i8 64}
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!1 = !{}
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!2 = !{i64 -2048, i64 1024}
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!3 = !{i128 -2048, i128 1024}
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!4 = !{i8 8, i8 64}

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