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RKSimonRKSimon
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[X86] Add missing immediate qualifier to the (V)EXTRACTPS instruction names
Makes it easier to algorithmically recreate the instruction name in various analysis scripts I'm working on
1 parent a56ca1a commit 7048857

12 files changed

+47
-47
lines changed

‎llvm/lib/Target/X86/X86InstrAVX512.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -998,13 +998,13 @@ defm : vextract_for_mask_cast<"VEXTRACTI64x4Z", v64i8_info, v32i8x_info,
998998
EXTRACT_get_vextract256_imm, [HasAVX512]>;
999999

10001000
// vextractps - extract 32 bits from XMM
1001-
def VEXTRACTPSZrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32orGR64:$dst),
1001+
def VEXTRACTPSZrri : AVX512AIi8<0x17, MRMDestReg, (outs GR32orGR64:$dst),
10021002
(ins VR128X:$src1, u8imm:$src2),
10031003
"vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
10041004
[(set GR32orGR64:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
10051005
EVEX, WIG, Sched<[WriteVecExtract]>;
10061006

1007-
def VEXTRACTPSZmr : AVX512AIi8<0x17, MRMDestMem, (outs),
1007+
def VEXTRACTPSZmri : AVX512AIi8<0x17, MRMDestMem, (outs),
10081008
(ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
10091009
"vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
10101010
[(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),

‎llvm/lib/Target/X86/X86InstrSSE.td

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -5333,19 +5333,19 @@ defm PEXTRQ : SS41I_extract64<0x16, "pextrq">, REX_W;
53335333
/// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
53345334
/// destination
53355335
multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5336-
def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
5337-
(ins VR128:$src1, u8imm:$src2),
5338-
!strconcat(OpcodeStr,
5339-
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5340-
[(set GR32orGR64:$dst,
5341-
(extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5342-
Sched<[WriteVecExtract]>;
5343-
def mr : SS4AIi8<opc, MRMDestMem, (outs),
5344-
(ins f32mem:$dst, VR128:$src1, u8imm:$src2),
5345-
!strconcat(OpcodeStr,
5346-
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5347-
[(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
5348-
addr:$dst)]>, Sched<[WriteVecExtractSt]>;
5336+
def rri : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
5337+
(ins VR128:$src1, u8imm:$src2),
5338+
!strconcat(OpcodeStr,
5339+
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5340+
[(set GR32orGR64:$dst,
5341+
(extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5342+
Sched<[WriteVecExtract]>;
5343+
def mri : SS4AIi8<opc, MRMDestMem, (outs),
5344+
(ins f32mem:$dst, VR128:$src1, u8imm:$src2),
5345+
!strconcat(OpcodeStr,
5346+
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5347+
[(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
5348+
addr:$dst)]>, Sched<[WriteVecExtractSt]>;
53495349
}
53505350

53515351
let ExeDomain = SSEPackedSingle in {

‎llvm/lib/Target/X86/X86ReplaceableInstrs.def

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -42,8 +42,8 @@ ENTRY(UNPCKLPSrm, UNPCKLPSrm, PUNPCKLDQrm)
4242
ENTRY(UNPCKLPSrr, UNPCKLPSrr, PUNPCKLDQrr)
4343
ENTRY(UNPCKHPSrm, UNPCKHPSrm, PUNPCKHDQrm)
4444
ENTRY(UNPCKHPSrr, UNPCKHPSrr, PUNPCKHDQrr)
45-
ENTRY(EXTRACTPSmr, EXTRACTPSmr, PEXTRDmr)
46-
ENTRY(EXTRACTPSrr, EXTRACTPSrr, PEXTRDrr)
45+
ENTRY(EXTRACTPSmri, EXTRACTPSmri, PEXTRDmr)
46+
ENTRY(EXTRACTPSrri, EXTRACTPSrri, PEXTRDrr)
4747
// AVX 128-bit support
4848
ENTRY(VMOVAPSmr, VMOVAPDmr, VMOVDQAmr)
4949
ENTRY(VMOVAPSrm, VMOVAPDrm, VMOVDQArm)
@@ -74,8 +74,8 @@ ENTRY(VUNPCKLPSrm, VUNPCKLPSrm, VPUNPCKLDQrm)
7474
ENTRY(VUNPCKLPSrr, VUNPCKLPSrr, VPUNPCKLDQrr)
7575
ENTRY(VUNPCKHPSrm, VUNPCKHPSrm, VPUNPCKHDQrm)
7676
ENTRY(VUNPCKHPSrr, VUNPCKHPSrr, VPUNPCKHDQrr)
77-
ENTRY(VEXTRACTPSmr, VEXTRACTPSmr, VPEXTRDmr)
78-
ENTRY(VEXTRACTPSrr, VEXTRACTPSrr, VPEXTRDrr)
77+
ENTRY(VEXTRACTPSmri, VEXTRACTPSmri, VPEXTRDmr)
78+
ENTRY(VEXTRACTPSrri, VEXTRACTPSrri, VPEXTRDrr)
7979
// AVX 256-bit support
8080
ENTRY(VMOVAPSYmr, VMOVAPDYmr, VMOVDQAYmr)
8181
ENTRY(VMOVAPSYrm, VMOVAPDYrm, VMOVDQAYrm)
@@ -178,8 +178,8 @@ ENTRY(VUNPCKLPSZrm, VUNPCKLPSZrm, VPUNPCKLDQZrm)
178178
ENTRY(VUNPCKLPSZrr, VUNPCKLPSZrr, VPUNPCKLDQZrr)
179179
ENTRY(VUNPCKHPSZrm, VUNPCKHPSZrm, VPUNPCKHDQZrm)
180180
ENTRY(VUNPCKHPSZrr, VUNPCKHPSZrr, VPUNPCKHDQZrr)
181-
ENTRY(VEXTRACTPSZmr, VEXTRACTPSZmr, VPEXTRDZmr)
182-
ENTRY(VEXTRACTPSZrr, VEXTRACTPSZrr, VPEXTRDZrr)
181+
ENTRY(VEXTRACTPSZmri, VEXTRACTPSZmri, VPEXTRDZmr)
182+
ENTRY(VEXTRACTPSZrri, VEXTRACTPSZrri, VPEXTRDZrr)
183183
};
184184

185185
static const uint16_t ReplaceableInstrsAVX2[][3] = {

‎llvm/lib/Target/X86/X86SchedAlderlakeP.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -886,14 +886,14 @@ def ADLPWriteResGroup50 : SchedWriteRes<[ADLPPort04_09, ADLPPort05, ADLPPort07_0
886886
let Latency = 12;
887887
let NumMicroOps = 3;
888888
}
889-
def : InstRW<[ADLPWriteResGroup50], (instregex "^(V?)EXTRACTPSmr$")>;
889+
def : InstRW<[ADLPWriteResGroup50], (instregex "^(V?)EXTRACTPSmri$")>;
890890
def : InstRW<[ADLPWriteResGroup50], (instrs SMSW16m)>;
891891

892892
def ADLPWriteResGroup51 : SchedWriteRes<[ADLPPort00, ADLPPort05]> {
893893
let Latency = 4;
894894
let NumMicroOps = 2;
895895
}
896-
def : InstRW<[ADLPWriteResGroup51], (instregex "^(V?)EXTRACTPSrr$")>;
896+
def : InstRW<[ADLPWriteResGroup51], (instregex "^(V?)EXTRACTPSrri$")>;
897897
def : InstRW<[ADLPWriteResGroup51], (instrs MMX_PEXTRWrr)>;
898898

899899
def ADLPWriteResGroup52 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort02_03, ADLPPort02_03_07, ADLPPort04, ADLPPort06]> {

‎llvm/lib/Target/X86/X86SchedIceLake.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -884,7 +884,7 @@ def ICXWriteResGroup36 : SchedWriteRes<[ICXPort0,ICXPort5]> {
884884
let NumMicroOps = 2;
885885
let ReleaseAtCycles = [1,1];
886886
}
887-
def: InstRW<[ICXWriteResGroup36], (instregex "(V?)EXTRACTPS(Z?)rr")>;
887+
def: InstRW<[ICXWriteResGroup36], (instregex "(V?)EXTRACTPS(Z?)rri")>;
888888

889889
def ICXWriteResGroup37 : SchedWriteRes<[ICXPort0,ICXPort5]> {
890890
let Latency = 3;
@@ -1034,7 +1034,7 @@ def ICXWriteResGroup53 : SchedWriteRes<[ICXPort49,ICXPort5,ICXPort78]> {
10341034
let NumMicroOps = 3;
10351035
let ReleaseAtCycles = [1,1,1];
10361036
}
1037-
def: InstRW<[ICXWriteResGroup53], (instregex "(V?)EXTRACTPS(Z?)mr")>;
1037+
def: InstRW<[ICXWriteResGroup53], (instregex "(V?)EXTRACTPS(Z?)mri")>;
10381038

10391039
def ICXWriteResGroup54 : SchedWriteRes<[ICXPort49,ICXPort5,ICXPort78]> {
10401040
let Latency = 4;

‎llvm/lib/Target/X86/X86SchedSandyBridge.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -686,7 +686,7 @@ def SBWriteResGroup22 : SchedWriteRes<[SBPort0,SBPort5]> {
686686
let NumMicroOps = 2;
687687
let ReleaseAtCycles = [1,1];
688688
}
689-
def: InstRW<[SBWriteResGroup22], (instregex "(V?)EXTRACTPSrr")>;
689+
def: InstRW<[SBWriteResGroup22], (instregex "(V?)EXTRACTPSrri")>;
690690

691691
def SBWriteResGroup23 : SchedWriteRes<[SBPort05,SBPort015]> {
692692
let Latency = 2;
@@ -789,7 +789,7 @@ def SBWriteResGroup36 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> {
789789
}
790790
def: InstRW<[SBWriteResGroup36], (instrs CALL64pcrel32)>;
791791
def: InstRW<[SBWriteResGroup36], (instregex "CALL(16|32|64)r",
792-
"(V?)EXTRACTPSmr")>;
792+
"(V?)EXTRACTPSmri")>;
793793

794794
def SBWriteResGroup40 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
795795
let Latency = 5;

‎llvm/lib/Target/X86/X86SchedSapphireRapids.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1004,18 +1004,18 @@ def SPRWriteResGroup54 : SchedWriteRes<[SPRPort04_09, SPRPort05, SPRPort07_08]>
10041004
let Latency = 12;
10051005
let NumMicroOps = 3;
10061006
}
1007-
def : InstRW<[SPRWriteResGroup54], (instregex "^(V?)EXTRACTPSmr$",
1007+
def : InstRW<[SPRWriteResGroup54], (instregex "^(V?)EXTRACTPSmri$",
10081008
"^VPMOVQDZ((256)?)mr$")>;
10091009
def : InstRW<[SPRWriteResGroup54], (instrs SMSW16m,
1010-
VEXTRACTPSZmr)>;
1010+
VEXTRACTPSZmri)>;
10111011

10121012
def SPRWriteResGroup55 : SchedWriteRes<[SPRPort00, SPRPort05]> {
10131013
let Latency = 4;
10141014
let NumMicroOps = 2;
10151015
}
1016-
def : InstRW<[SPRWriteResGroup55], (instregex "^(V?)EXTRACTPSrr$")>;
1016+
def : InstRW<[SPRWriteResGroup55], (instregex "^(V?)EXTRACTPSrri$")>;
10171017
def : InstRW<[SPRWriteResGroup55], (instrs MMX_PEXTRWrr,
1018-
VEXTRACTPSZrr,
1018+
VEXTRACTPSZrri,
10191019
VPERMWZrr)>;
10201020

10211021
def SPRWriteResGroup56 : SchedWriteRes<[SPRPort02_03, SPRPort02_03_11, SPRPort04, SPRPort04_09, SPRPort06]> {

‎llvm/lib/Target/X86/X86ScheduleZnver1.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1017,15 +1017,15 @@ def ZnWriteEXTRACTPSr : SchedWriteRes<[ZnFPU12, ZnFPU2]> {
10171017
let NumMicroOps = 2;
10181018
let ReleaseAtCycles = [1, 2];
10191019
}
1020-
def : InstRW<[ZnWriteEXTRACTPSr], (instregex "(V?)EXTRACTPSrr")>;
1020+
def : InstRW<[ZnWriteEXTRACTPSr], (instregex "(V?)EXTRACTPSrri")>;
10211021

10221022
def ZnWriteEXTRACTPSm : SchedWriteRes<[ZnAGU,ZnFPU12, ZnFPU2]> {
10231023
let Latency = 5;
10241024
let NumMicroOps = 2;
10251025
let ReleaseAtCycles = [5, 1, 2];
10261026
}
10271027
// m32,x,i.
1028-
def : InstRW<[ZnWriteEXTRACTPSm], (instregex "(V?)EXTRACTPSmr")>;
1028+
def : InstRW<[ZnWriteEXTRACTPSm], (instregex "(V?)EXTRACTPSmri")>;
10291029

10301030
// VEXTRACTF128 / VEXTRACTI128.
10311031
// x,y,i.

‎llvm/lib/Target/X86/X86ScheduleZnver2.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1023,15 +1023,15 @@ def Zn2WriteEXTRACTPSr : SchedWriteRes<[Zn2FPU12, Zn2FPU2]> {
10231023
let NumMicroOps = 2;
10241024
let ReleaseAtCycles = [1, 2];
10251025
}
1026-
def : InstRW<[Zn2WriteEXTRACTPSr], (instregex "(V?)EXTRACTPSrr")>;
1026+
def : InstRW<[Zn2WriteEXTRACTPSr], (instregex "(V?)EXTRACTPSrri")>;
10271027

10281028
def Zn2WriteEXTRACTPSm : SchedWriteRes<[Zn2AGU,Zn2FPU12, Zn2FPU2]> {
10291029
let Latency = 5;
10301030
let NumMicroOps = 2;
10311031
let ReleaseAtCycles = [5, 1, 2];
10321032
}
10331033
// m32,x,i.
1034-
def : InstRW<[Zn2WriteEXTRACTPSm], (instregex "(V?)EXTRACTPSmr")>;
1034+
def : InstRW<[Zn2WriteEXTRACTPSm], (instregex "(V?)EXTRACTPSmri")>;
10351035

10361036
// VEXTRACTF128 / VEXTRACTI128.
10371037
// x,y,i.

‎llvm/test/CodeGen/X86/evex-to-vex-compress.mir

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2300,10 +2300,10 @@ body: |
23002300
VUCOMISSZrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
23012301
; CHECK: VUCOMISSrr $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
23022302
VUCOMISSZrr $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2303-
; CHECK: VEXTRACTPSmr $rdi, 1, $noreg, 0, $noreg, $xmm0, 1
2304-
VEXTRACTPSZmr $rdi, 1, $noreg, 0, $noreg, $xmm0, 1
2305-
; CHECK: $eax = VEXTRACTPSrr $xmm0, 1
2306-
$eax = VEXTRACTPSZrr $xmm0, 1
2303+
; CHECK: VEXTRACTPSmri $rdi, 1, $noreg, 0, $noreg, $xmm0, 1
2304+
VEXTRACTPSZmri $rdi, 1, $noreg, 0, $noreg, $xmm0, 1
2305+
; CHECK: $eax = VEXTRACTPSrri $xmm0, 1
2306+
$eax = VEXTRACTPSZrri $xmm0, 1
23072307
; CHECK: $xmm0 = VINSERTPSrmi $xmm0, $rdi, 1, $noreg, 0, $noreg, 1
23082308
$xmm0 = VINSERTPSZrmi $xmm0, $rdi, 1, $noreg, 0, $noreg, 1
23092309
; CHECK: $xmm0 = VINSERTPSrri $xmm0, $xmm0, 1
@@ -4068,10 +4068,10 @@ body: |
40684068
$xmm16 = VPALIGNRZ128rmi $xmm16, $rdi, 1, $noreg, 0, $noreg, 15
40694069
; CHECK: $xmm16 = VPALIGNRZ128rri $xmm16, $xmm1, 15
40704070
$xmm16 = VPALIGNRZ128rri $xmm16, $xmm1, 15
4071-
; CHECK: VEXTRACTPSZmr $rdi, 1, $noreg, 0, $noreg, $xmm16, 1
4072-
VEXTRACTPSZmr $rdi, 1, $noreg, 0, $noreg, $xmm16, 1
4073-
; CHECK: $eax = VEXTRACTPSZrr $xmm16, 1
4074-
$eax = VEXTRACTPSZrr $xmm16, 1
4071+
; CHECK: VEXTRACTPSZmri $rdi, 1, $noreg, 0, $noreg, $xmm16, 1
4072+
VEXTRACTPSZmri $rdi, 1, $noreg, 0, $noreg, $xmm16, 1
4073+
; CHECK: $eax = VEXTRACTPSZrri $xmm16, 1
4074+
$eax = VEXTRACTPSZrri $xmm16, 1
40754075
; CHECK: $xmm16 = VINSERTPSZrmi $xmm16, $rdi, 1, $noreg, 0, $noreg, 1
40764076
$xmm16 = VINSERTPSZrmi $xmm16, $rdi, 1, $noreg, 0, $noreg, 1
40774077
; CHECK: $xmm16 = VINSERTPSZrri $xmm16, $xmm16, 1

‎llvm/test/CodeGen/X86/vmaskmov-offset.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -76,7 +76,7 @@ define void @one_mask_bit_set2(ptr %addr, <4 x float> %val) {
7676
; CHECK-NEXT: {{ $}}
7777
; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
7878
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
79-
; CHECK-NEXT: VEXTRACTPSmr [[COPY1]], 1, $noreg, 8, $noreg, [[COPY]], 2 :: (store (s32) into %ir.addr + 8)
79+
; CHECK-NEXT: VEXTRACTPSmri [[COPY1]], 1, $noreg, 8, $noreg, [[COPY]], 2 :: (store (s32) into %ir.addr + 8)
8080
; CHECK-NEXT: RET 0
8181
call void @llvm.masked.store.v4f32.p0(<4 x float> %val, ptr %addr, i32 4, <4 x i1><i1 false, i1 false, i1 true, i1 false>)
8282
ret void

‎llvm/test/TableGen/x86-fold-tables.inc

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -402,7 +402,7 @@ static const X86FoldTableEntry Table0[] = {
402402
{X86::DIV64r_NF, X86::DIV64m_NF, TB_FOLDED_LOAD},
403403
{X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD},
404404
{X86::DIV8r_NF, X86::DIV8m_NF, TB_FOLDED_LOAD},
405-
{X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE},
405+
{X86::EXTRACTPSrri, X86::EXTRACTPSmri, TB_FOLDED_STORE},
406406
{X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD},
407407
{X86::IDIV16r_NF, X86::IDIV16m_NF, TB_FOLDED_LOAD},
408408
{X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD},
@@ -500,8 +500,8 @@ static const X86FoldTableEntry Table0[] = {
500500
{X86::VEXTRACTI64x2Z256rri, X86::VEXTRACTI64x2Z256mri, TB_FOLDED_STORE},
501501
{X86::VEXTRACTI64x2Zrri, X86::VEXTRACTI64x2Zmri, TB_FOLDED_STORE},
502502
{X86::VEXTRACTI64x4Zrri, X86::VEXTRACTI64x4Zmri, TB_FOLDED_STORE},
503-
{X86::VEXTRACTPSZrr, X86::VEXTRACTPSZmr, TB_FOLDED_STORE},
504-
{X86::VEXTRACTPSrr, X86::VEXTRACTPSmr, TB_FOLDED_STORE},
503+
{X86::VEXTRACTPSZrri, X86::VEXTRACTPSZmri, TB_FOLDED_STORE},
504+
{X86::VEXTRACTPSrri, X86::VEXTRACTPSmri, TB_FOLDED_STORE},
505505
{X86::VMOV64toSDZrr, X86::MOV64mr, TB_FOLDED_STORE|TB_NO_REVERSE},
506506
{X86::VMOV64toSDrr, X86::MOV64mr, TB_FOLDED_STORE|TB_NO_REVERSE},
507507
{X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE|TB_NO_REVERSE|TB_ALIGN_32},

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