Revert rG528bc10e95d5f9d6a338f9bab5e91d7265d1cf05 : "[X86FixupLEAs] Transform the sequence LEA/SUB to SUB/SUB"

Reports on D101970 indicate this is causing failures on multi-stage compiles.

Author: RKSimon

llvm/include/llvm/CodeGen/TargetInstrInfo.h

@@ -459,13 +459,6 @@ class TargetInstrInfo : public MCInstrInfo {
                                      unsigned &SrcOpIdx1,
                                      unsigned &SrcOpIdx2) const;
 
-  /// Returns true if the target has a preference on the operands order of
-  /// the given machine instruction. And specify if \p Commute is required to
-  /// get the desired operands order.
-  virtual bool hasCommutePreference(MachineInstr &MI, bool &Commute) const {
-    return false;
-  }
-
   /// A pair composed of a register and a sub-register index.
   /// Used to give some type checking when modeling Reg:SubReg.
   struct RegSubRegPair {

llvm/lib/CodeGen/TwoAddressInstructionPass.cpp

@@ -527,11 +527,6 @@ bool TwoAddressInstructionPass::isProfitableToCommute(Register RegA,
   if (isRevCopyChain(RegB, RegA, MaxDataFlowEdge))
     return false;
 
-  // Look for other target specific commute preference.
-  bool Commute;
-  if (TII->hasCommutePreference(*MI, Commute))
-    return Commute;
-
   // Since there are no intervening uses for both registers, then commute
   // if the def of RegC is closer. Its live interval is shorter.
   return LastDefB && LastDefC && LastDefC > LastDefB;

llvm/lib/Target/X86/X86FixupLEAs.cpp

@@ -79,27 +79,6 @@ class FixupLEAPass : public MachineFunctionPass {
                      MachineBasicBlock &MBB, bool OptIncDec,
                      bool UseLEAForSP) const;
 
-  /// Look for and transform the sequence
-  ///     lea (reg1, reg2), reg3
-  ///     sub reg3, reg4
-  /// to
-  ///     sub reg1, reg4
-  ///     sub reg2, reg4
-  /// It can also optimize the sequence lea/add similarly.
-  bool optLEAALU(MachineBasicBlock::iterator &I, MachineBasicBlock &MBB) const;
-
-  /// Step forwards in MBB, looking for an ADD/SUB instruction which uses
-  /// the dest register of LEA instruction I.
-  MachineBasicBlock::iterator searchALUInst(MachineBasicBlock::iterator &I,
-                                            MachineBasicBlock &MBB) const;
-
-  /// Check instructions between LeaI and AluI (exclusively).
-  /// Set BaseIndexDef to true if base or index register from LeaI is defined.
-  /// Set AluDestRef to true if the dest register of AluI is used or defined.
-  void checkRegUsage(MachineBasicBlock::iterator &LeaI,
-                     MachineBasicBlock::iterator &AluI, bool &BaseIndexDef,
-                     bool &AluDestRef) const;
-
   /// Determine if an instruction references a machine register
   /// and, if so, whether it reads or writes the register.
   RegUsageState usesRegister(MachineOperand &p, MachineBasicBlock::iterator I);
@@ -359,18 +338,6 @@ static inline unsigned getADDrrFromLEA(unsigned LEAOpcode) {
   }
 }
 
-static inline unsigned getSUBrrFromLEA(unsigned LEAOpcode) {
-  switch (LEAOpcode) {
-  default:
-    llvm_unreachable("Unexpected LEA instruction");
-  case X86::LEA32r:
-  case X86::LEA64_32r:
-    return X86::SUB32rr;
-  case X86::LEA64r:
-    return X86::SUB64rr;
-  }
-}
-
 static inline unsigned getADDriFromLEA(unsigned LEAOpcode,
                                        const MachineOperand &Offset) {
   bool IsInt8 = Offset.isImm() && isInt<8>(Offset.getImm());
@@ -397,133 +364,6 @@ static inline unsigned getINCDECFromLEA(unsigned LEAOpcode, bool IsINC) {
   }
 }
 
-MachineBasicBlock::iterator
-FixupLEAPass::searchALUInst(MachineBasicBlock::iterator &I,
-                            MachineBasicBlock &MBB) const {
-  const int InstrDistanceThreshold = 5;
-  int InstrDistance = 1;
-  MachineBasicBlock::iterator CurInst = std::next(I);
-
-  unsigned LEAOpcode = I->getOpcode();
-  unsigned AddOpcode = getADDrrFromLEA(LEAOpcode);
-  unsigned SubOpcode = getSUBrrFromLEA(LEAOpcode);
-  Register DestReg = I->getOperand(0).getReg();
-
-  while (CurInst != MBB.end()) {
-    if (CurInst->isCall() || CurInst->isInlineAsm())
-      break;
-    if (InstrDistance > InstrDistanceThreshold)
-      break;
-
-    // Check if the lea dest register is used in an add/sub instruction only.
-    for (unsigned I = 0, E = CurInst->getNumOperands(); I != E; ++I) {
-      MachineOperand &Opnd = CurInst->getOperand(I);
-      if (Opnd.isReg() && Opnd.getReg() == DestReg) {
-        if (Opnd.isDef() || !Opnd.isKill())
-          return MachineBasicBlock::iterator();
-
-        unsigned AluOpcode = CurInst->getOpcode();
-        if (AluOpcode != AddOpcode && AluOpcode != SubOpcode)
-          return MachineBasicBlock::iterator();
-
-        MachineOperand &Opnd2 = CurInst->getOperand(3 - I);
-        MachineOperand AluDest = CurInst->getOperand(0);
-        if (Opnd2.getReg() != AluDest.getReg())
-          return MachineBasicBlock::iterator();
-
-        return CurInst;
-      }
-    }
-
-    InstrDistance++;
-    ++CurInst;
-  }
-  return MachineBasicBlock::iterator();
-}
-
-void FixupLEAPass::checkRegUsage(MachineBasicBlock::iterator &LeaI,
-                                 MachineBasicBlock::iterator &AluI,
-                                 bool &BaseIndexDef, bool &AluDestRef) const {
-  BaseIndexDef = AluDestRef = false;
-  Register BaseReg = LeaI->getOperand(1 + X86::AddrBaseReg).getReg();
-  Register IndexReg = LeaI->getOperand(1 + X86::AddrIndexReg).getReg();
-  Register AluDestReg = AluI->getOperand(0).getReg();
-
-  MachineBasicBlock::iterator CurInst = std::next(LeaI);
-  while (CurInst != AluI) {
-    for (unsigned I = 0, E = CurInst->getNumOperands(); I != E; ++I) {
-      MachineOperand &Opnd = CurInst->getOperand(I);
-      if (!Opnd.isReg())
-        continue;
-      Register Reg = Opnd.getReg();
-      if (TRI->regsOverlap(Reg, AluDestReg))
-        AluDestRef = true;
-      if (Opnd.isDef() &&
-          (TRI->regsOverlap(Reg, BaseReg) || TRI->regsOverlap(Reg, IndexReg))) {
-        BaseIndexDef = true;
-      }
-    }
-    ++CurInst;
-  }
-}
-
-bool FixupLEAPass::optLEAALU(MachineBasicBlock::iterator &I,
-                             MachineBasicBlock &MBB) const {
-  // Look for an add/sub instruction which uses the result of lea.
-  MachineBasicBlock::iterator AluI = searchALUInst(I, MBB);
-  if (AluI == MachineBasicBlock::iterator())
-    return false;
-
-  // Check if there are any related register usage between lea and alu.
-  bool BaseIndexDef, AluDestRef;
-  checkRegUsage(I, AluI, BaseIndexDef, AluDestRef);
-
-  MachineBasicBlock::iterator InsertPos = AluI;
-  if (BaseIndexDef) {
-    if (AluDestRef)
-      return false;
-    MachineBasicBlock::iterator AfterAluI = std::next(AluI);
-    if (MBB.computeRegisterLiveness(TRI, X86::EFLAGS, AfterAluI) !=
-        MachineBasicBlock::LQR_Dead)
-      return false;
-
-    InsertPos = I;
-  }
-
-  // Check if there are same registers.
-  Register AluDestReg = AluI->getOperand(0).getReg();
-  Register BaseReg = I->getOperand(1 + X86::AddrBaseReg).getReg();
-  Register IndexReg = I->getOperand(1 + X86::AddrIndexReg).getReg();
-  if (I->getOpcode() == X86::LEA64_32r) {
-    BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);
-    IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit);
-  }
-  if (AluDestReg == IndexReg) {
-    if (BaseReg == IndexReg)
-      return false;
-    std::swap(BaseReg, IndexReg);
-  }
-
-  // Now it's safe to change instructions.
-  MachineInstr *NewMI1, *NewMI2;
-  unsigned NewOpcode = AluI->getOpcode();
-  NewMI1 = BuildMI(MBB, InsertPos, AluI->getDebugLoc(), TII->get(NewOpcode),
-                   AluDestReg)
-               .addReg(AluDestReg)
-               .addReg(BaseReg);
-  NewMI2 = BuildMI(MBB, InsertPos, AluI->getDebugLoc(), TII->get(NewOpcode),
-                   AluDestReg)
-               .addReg(AluDestReg)
-               .addReg(IndexReg);
-
-  MBB.getParent()->substituteDebugValuesForInst(*AluI, *NewMI1, 1);
-  MBB.getParent()->substituteDebugValuesForInst(*AluI, *NewMI2, 1);
-  MBB.erase(I);
-  MBB.erase(AluI);
-  I = NewMI1;
-  return true;
-}
-
 bool FixupLEAPass::optTwoAddrLEA(MachineBasicBlock::iterator &I,
                                  MachineBasicBlock &MBB, bool OptIncDec,
                                  bool UseLEAForSP) const {
@@ -558,7 +398,6 @@ bool FixupLEAPass::optTwoAddrLEA(MachineBasicBlock::iterator &I,
 
   MachineInstr *NewMI = nullptr;
 
-  // Case 1.
   // Look for lea(%reg1, %reg2), %reg1 or lea(%reg2, %reg1), %reg1
   // which can be turned into add %reg2, %reg1
   if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 &&
@@ -578,7 +417,6 @@ bool FixupLEAPass::optTwoAddrLEA(MachineBasicBlock::iterator &I,
         .addReg(BaseReg).addReg(IndexReg);
     }
   } else if (DestReg == BaseReg && IndexReg == 0) {
-    // Case 2.
     // This is an LEA with only a base register and a displacement,
     // We can use ADDri or INC/DEC.
 
@@ -609,12 +447,6 @@ bool FixupLEAPass::optTwoAddrLEA(MachineBasicBlock::iterator &I,
           .addReg(BaseReg).addImm(Disp.getImm());
       }
     }
-  } else if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0) {
-    // Case 3.
-    // Look for and transform the sequence
-    //     lea (reg1, reg2), reg3
-    //     sub reg3, reg4
-    return optLEAALU(I, MBB);
   } else
     return false;
 

llvm/lib/Target/X86/X86InstrInfo.cpp

@@ -2670,60 +2670,6 @@ bool X86InstrInfo::findCommutedOpIndices(const MachineInstr &MI,
   return false;
 }
 
-static bool isConvertibleLEA(MachineInstr *MI) {
-  unsigned Opcode = MI->getOpcode();
-  if (Opcode != X86::LEA32r && Opcode != X86::LEA64r &&
-      Opcode != X86::LEA64_32r)
-    return false;
-
-  const MachineOperand &Scale = MI->getOperand(1 + X86::AddrScaleAmt);
-  const MachineOperand &Disp = MI->getOperand(1 + X86::AddrDisp);
-  const MachineOperand &Segment = MI->getOperand(1 + X86::AddrSegmentReg);
-
-  if (Segment.getReg() != 0 || !Disp.isImm() || Disp.getImm() != 0 ||
-      Scale.getImm() > 1)
-    return false;
-
-  return true;
-}
-
-bool X86InstrInfo::hasCommutePreference(MachineInstr &MI, bool &Commute) const {
-  // Currently we're interested in following sequence only.
-  //   r3 = lea r1, r2
-  //   r5 = add r3, r4
-  // Both r3 and r4 are killed in add, we hope the add instruction has the
-  // operand order
-  //   r5 = add r4, r3
-  // So later in X86FixupLEAs the lea instruction can be rewritten as add.
-  unsigned Opcode = MI.getOpcode();
-  if (Opcode != X86::ADD32rr && Opcode != X86::ADD64rr)
-    return false;
-
-  const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
-  Register Reg1 = MI.getOperand(1).getReg();
-  Register Reg2 = MI.getOperand(2).getReg();
-
-  // Check if Reg1 comes from LEA in the same MBB.
-  if (MachineOperand *Op = MRI.getOneDef(Reg1)) {
-    MachineInstr *Inst = Op->getParent();
-    if (isConvertibleLEA(Inst) && Inst->getParent() == MI.getParent()) {
-      Commute = true;
-      return true;
-    }
-  }
-
-  // Check if Reg2 comes from LEA in the same MBB.
-  if (MachineOperand *Op = MRI.getOneDef(Reg2)) {
-    MachineInstr *Inst = Op->getParent();
-    if (isConvertibleLEA(Inst) && Inst->getParent() == MI.getParent()) {
-      Commute = false;
-      return true;
-    }
-  }
-
-  return false;
-}
-
 X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
   switch (MI.getOpcode()) {
   default: return X86::COND_INVALID;

llvm/lib/Target/X86/X86InstrInfo.h

@@ -284,10 +284,6 @@ class X86InstrInfo final : public X86GenInstrInfo {
   bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
                              unsigned &SrcOpIdx2) const override;
 
-  /// Returns true if we have preference on the operands order in MI, the
-  /// commute decision is returned in Commute.
-  bool hasCommutePreference(MachineInstr &MI, bool &Commute) const override;
-
   /// Returns an adjusted FMA opcode that must be used in FMA instruction that
   /// performs the same computations as the given \p MI but which has the
   /// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted.