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Jessica Paquette
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[GlobalISel] Import patterns containing SUBREG_TO_REG
Reuse the logic for INSERT_SUBREG to also import SUBREG_TO_REG patterns. - Split `inferSuperRegisterClass` into two functions, one which tries to use an existing TreePatternNode (`inferSuperRegisterClassForNode`), and one that doesn't. SUBREG_TO_REG doesn't have a node to leverage, which is the cause for the split. - Rename GlobalISelEmitterInsertSubreg.td to GlobalISelEmitterSubreg.td and update it. - Update impacted tests in the AArch64 and X86 backends. This is kind of a hit/miss for code size improvements/regressions. E.g. in add-ext.ll, we now get some identity copies. This isn't really anything the importer can handle, since it's caused by a later pass introducing the copy for the sake of correctness. Differential Revision: https://reviews.llvm.org/D66769 llvm-svn: 370254
1 parent 6acfc7c commit 7080ffa

15 files changed

+258
-153
lines changed

‎llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -286,8 +286,9 @@ body: |
286286
; CHECK-LABEL: name: mul_not_pow_2
287287
; CHECK: liveins: $x0, $x1, $d2
288288
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
289-
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 7
290-
; CHECK: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[MOVi64imm]], [[COPY]], $xzr
289+
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 7
290+
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
291+
; CHECK: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[SUBREG_TO_REG]], [[COPY]], $xzr
291292
; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1
292293
; CHECK: [[LDRDroX:%[0-9]+]]:fpr64 = LDRDroX [[COPY1]], [[MADDXrrr]], 0, 0 :: (load 8 from %ir.addr)
293294
; CHECK: $d2 = COPY [[LDRDroX]]
@@ -317,8 +318,9 @@ body: |
317318
; CHECK-LABEL: name: mul_wrong_pow_2
318319
; CHECK: liveins: $x0, $x1, $d2
319320
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
320-
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 16
321-
; CHECK: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[MOVi64imm]], [[COPY]], $xzr
321+
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 16
322+
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
323+
; CHECK: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[SUBREG_TO_REG]], [[COPY]], $xzr
322324
; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1
323325
; CHECK: [[LDRDroX:%[0-9]+]]:fpr64 = LDRDroX [[COPY1]], [[MADDXrrr]], 0, 0 :: (load 8 from %ir.addr)
324326
; CHECK: $d2 = COPY [[LDRDroX]]

‎llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir

Lines changed: 49 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -44,10 +44,10 @@ body: |
4444
; CHECK: liveins: $w0, $w1
4545
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
4646
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
47-
; CHECK: [[MOVwzr:%[0-9]+]]:gpr32 = COPY $wzr
48-
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
47+
; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
48+
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
4949
; CHECK: $wzr = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
50-
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVwzr]], 1, implicit $nzcv
50+
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY2]], 1, implicit $nzcv
5151
; CHECK: $w0 = COPY [[CSELWr]]
5252
; CHECK: RET_ReallyLR implicit $w0
5353
%0:gpr(s32) = COPY $w0
@@ -76,10 +76,10 @@ body: |
7676
; CHECK: liveins: $w0, $w1
7777
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
7878
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
79-
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = COPY $wzr
80-
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
79+
; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
80+
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
8181
; CHECK: $wzr = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
82-
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 1, implicit $nzcv
82+
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY2]], 1, implicit $nzcv
8383
; CHECK: $w0 = COPY [[CSELWr]]
8484
; CHECK: RET_ReallyLR implicit $w0
8585
%0:gpr(s32) = COPY $w0
@@ -108,11 +108,11 @@ body: |
108108
; CHECK: liveins: $w0, $w1
109109
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
110110
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
111-
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = COPY $wzr
112-
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
113-
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[MOVi32imm]], [[COPY1]], implicit-def $nzcv
111+
; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
112+
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
113+
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY2]], [[COPY1]], implicit-def $nzcv
114114
; CHECK: $wzr = SUBSWrr [[COPY]], [[SUBSWrr]], implicit-def $nzcv
115-
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 11, implicit $nzcv
115+
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY2]], 11, implicit $nzcv
116116
; CHECK: $w0 = COPY [[CSELWr]]
117117
; CHECK: RET_ReallyLR implicit $w0
118118
%0:gpr(s32) = COPY $w0
@@ -141,11 +141,11 @@ body: |
141141
; CHECK: liveins: $w0, $w1
142142
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
143143
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
144-
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = COPY $wzr
145-
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
146-
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[MOVi32imm]], [[COPY]], implicit-def $nzcv
144+
; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
145+
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
146+
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY2]], [[COPY]], implicit-def $nzcv
147147
; CHECK: $wzr = SUBSWrr [[SUBSWrr]], [[COPY1]], implicit-def $nzcv
148-
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 11, implicit $nzcv
148+
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY2]], 11, implicit $nzcv
149149
; CHECK: $w0 = COPY [[CSELWr]]
150150
; CHECK: RET_ReallyLR implicit $w0
151151
%0:gpr(s32) = COPY $w0
@@ -174,10 +174,11 @@ body: |
174174
; CHECK: liveins: $x0, $x1
175175
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
176176
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
177-
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = COPY $xzr
178-
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1
177+
; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr
178+
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
179+
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
179180
; CHECK: $xzr = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
180-
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 1, implicit $nzcv
181+
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[SUBREG_TO_REG]], [[COPY2]], 1, implicit $nzcv
181182
; CHECK: $x0 = COPY [[CSELXr]]
182183
; CHECK: RET_ReallyLR implicit $x0
183184
%0:gpr(s64) = COPY $x0
@@ -206,10 +207,11 @@ body: |
206207
; CHECK: liveins: $x0, $x1
207208
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
208209
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
209-
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = COPY $xzr
210-
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1
210+
; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr
211+
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
212+
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
211213
; CHECK: $xzr = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
212-
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 1, implicit $nzcv
214+
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[SUBREG_TO_REG]], [[COPY2]], 1, implicit $nzcv
213215
; CHECK: $x0 = COPY [[CSELXr]]
214216
; CHECK: RET_ReallyLR implicit $x0
215217
%0:gpr(s64) = COPY $x0
@@ -238,11 +240,12 @@ body: |
238240
; CHECK: liveins: $x0, $x1
239241
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
240242
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
241-
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = COPY $xzr
242-
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1
243-
; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[MOVi64imm]], [[COPY1]], implicit-def $nzcv
243+
; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr
244+
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
245+
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
246+
; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY2]], [[COPY1]], implicit-def $nzcv
244247
; CHECK: $xzr = SUBSXrr [[COPY]], [[SUBSXrr]], implicit-def $nzcv
245-
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 11, implicit $nzcv
248+
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[SUBREG_TO_REG]], [[COPY2]], 11, implicit $nzcv
246249
; CHECK: $x0 = COPY [[CSELXr]]
247250
; CHECK: RET_ReallyLR implicit $x0
248251
%0:gpr(s64) = COPY $x0
@@ -271,11 +274,12 @@ body: |
271274
; CHECK: liveins: $x0, $x1
272275
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
273276
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
274-
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = COPY $xzr
275-
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1
276-
; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[MOVi64imm]], [[COPY]], implicit-def $nzcv
277+
; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr
278+
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
279+
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
280+
; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY2]], [[COPY]], implicit-def $nzcv
277281
; CHECK: $xzr = SUBSXrr [[SUBSXrr]], [[COPY1]], implicit-def $nzcv
278-
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 11, implicit $nzcv
282+
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[SUBREG_TO_REG]], [[COPY2]], 11, implicit $nzcv
279283
; CHECK: $x0 = COPY [[CSELXr]]
280284
; CHECK: RET_ReallyLR implicit $x0
281285
%0:gpr(s64) = COPY $x0
@@ -302,10 +306,10 @@ body: |
302306
; CHECK-LABEL: name: tst_s32
303307
; CHECK: liveins: $w0, $w1
304308
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
305-
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = COPY $wzr
306-
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
307-
; CHECK: $wzr = ANDSWrr [[MOVi32imm]], [[COPY]], implicit-def $nzcv
308-
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 0, implicit $nzcv
309+
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
310+
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
311+
; CHECK: $wzr = ANDSWrr [[COPY1]], [[COPY]], implicit-def $nzcv
312+
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY1]], 0, implicit $nzcv
309313
; CHECK: $w0 = COPY [[CSELWr]]
310314
; CHECK: RET_ReallyLR implicit $w0
311315
%0:gpr(s32) = COPY $w0
@@ -333,10 +337,11 @@ body: |
333337
; CHECK-LABEL: name: tst_s64
334338
; CHECK: liveins: $x0, $x1
335339
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
336-
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = COPY $xzr
337-
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1
338-
; CHECK: $xzr = ANDSXrr [[MOVi64imm]], [[COPY]], implicit-def $nzcv
339-
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 0, implicit $nzcv
340+
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $xzr
341+
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
342+
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
343+
; CHECK: $xzr = ANDSXrr [[COPY1]], [[COPY]], implicit-def $nzcv
344+
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[SUBREG_TO_REG]], [[COPY1]], 0, implicit $nzcv
340345
; CHECK: $x0 = COPY [[CSELXr]]
341346
; CHECK: RET_ReallyLR implicit $x0
342347
%0:gpr(s64) = COPY $x0
@@ -364,11 +369,11 @@ body: |
364369
; CHECK-LABEL: name: no_tst_unsigned_compare
365370
; CHECK: liveins: $w0, $w1
366371
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
367-
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = COPY $wzr
368-
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
369-
; CHECK: [[ANDWrr:%[0-9]+]]:gpr32common = ANDWrr [[MOVi32imm]], [[COPY]]
372+
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
373+
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
374+
; CHECK: [[ANDWrr:%[0-9]+]]:gpr32common = ANDWrr [[COPY1]], [[COPY]]
370375
; CHECK: $wzr = SUBSWri [[ANDWrr]], 0, 0, implicit-def $nzcv
371-
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 8, implicit $nzcv
376+
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY1]], 8, implicit $nzcv
372377
; CHECK: $w0 = COPY [[CSELWr]]
373378
; CHECK: RET_ReallyLR implicit $w0
374379
%0:gpr(s32) = COPY $w0
@@ -396,11 +401,11 @@ body: |
396401
; CHECK-LABEL: name: no_tst_nonzero
397402
; CHECK: liveins: $w0, $w1
398403
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
399-
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = COPY $wzr
400-
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
401-
; CHECK: [[ANDWrr:%[0-9]+]]:gpr32common = ANDWrr [[MOVi32imm]], [[COPY]]
404+
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
405+
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
406+
; CHECK: [[ANDWrr:%[0-9]+]]:gpr32common = ANDWrr [[COPY1]], [[COPY]]
402407
; CHECK: $wzr = SUBSWri [[ANDWrr]], 42, 0, implicit-def $nzcv
403-
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 8, implicit $nzcv
408+
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY1]], 8, implicit $nzcv
404409
; CHECK: $w0 = COPY [[CSELWr]]
405410
; CHECK: RET_ReallyLR implicit $w0
406411
%0:gpr(s32) = COPY $w0

‎llvm/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir

Lines changed: 36 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -29,9 +29,10 @@ body: |
2929
3030
; CHECK-LABEL: name: atomicrmw_xchg_i64
3131
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
32-
; CHECK: [[CST:%[0-9]+]]:gpr64 = MOVi64imm 1
33-
; CHECK: [[RES:%[0-9]+]]:gpr64 = SWPX [[CST]], [[COPY]] :: (load store monotonic 8 on %ir.addr)
34-
; CHECK: $x0 = COPY [[RES]]
32+
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
33+
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
34+
; CHECK: [[SWPX:%[0-9]+]]:gpr64 = SWPX [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic 8 on %ir.addr)
35+
; CHECK: $x0 = COPY [[SWPX]]
3536
%0:gpr(p0) = COPY $x0
3637
%1:gpr(s64) = G_CONSTANT i64 1
3738
%2:gpr(s64) = G_ATOMICRMW_XCHG %0, %1 :: (load store monotonic 8 on %ir.addr)
@@ -48,9 +49,10 @@ body: |
4849
4950
; CHECK-LABEL: name: atomicrmw_add_i64
5051
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
51-
; CHECK: [[CST:%[0-9]+]]:gpr64 = MOVi64imm 1
52-
; CHECK: [[RES:%[0-9]+]]:gpr64 = LDADDX [[CST]], [[COPY]] :: (load store monotonic 8 on %ir.addr)
53-
; CHECK: $x0 = COPY [[RES]]
52+
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
53+
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
54+
; CHECK: [[LDADDX:%[0-9]+]]:gpr64 = LDADDX [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic 8 on %ir.addr)
55+
; CHECK: $x0 = COPY [[LDADDX]]
5456
%0:gpr(p0) = COPY $x0
5557
%1:gpr(s64) = G_CONSTANT i64 1
5658
%2:gpr(s64) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 8 on %ir.addr)
@@ -67,9 +69,9 @@ body: |
6769
6870
; CHECK-LABEL: name: atomicrmw_add_i32
6971
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
70-
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
71-
; CHECK: [[RES:%[0-9]+]]:gpr32 = LDADDALW [[CST]], [[COPY]] :: (load store seq_cst 4 on %ir.addr)
72-
; CHECK: $w0 = COPY [[RES]]
72+
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
73+
; CHECK: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[MOVi32imm]], [[COPY]] :: (load store seq_cst 4 on %ir.addr)
74+
; CHECK: $w0 = COPY [[LDADDALW]]
7375
%0:gpr(p0) = COPY $x0
7476
%1:gpr(s32) = G_CONSTANT i32 1
7577
%2:gpr(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4 on %ir.addr)
@@ -87,9 +89,9 @@ body: |
8789
8890
; CHECK-LABEL: name: atomicrmw_sub_i32
8991
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
90-
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
91-
; CHECK: [[RES:%[0-9]+]]:gpr32 = LDADDALW [[CST]], [[COPY]] :: (load store seq_cst 4 on %ir.addr)
92-
; CHECK: $w0 = COPY [[RES]]
92+
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
93+
; CHECK: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[MOVi32imm]], [[COPY]] :: (load store seq_cst 4 on %ir.addr)
94+
; CHECK: $w0 = COPY [[LDADDALW]]
9395
%0:gpr(p0) = COPY $x0
9496
%1:gpr(s32) = G_CONSTANT i32 1
9597
%2:gpr(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4 on %ir.addr)
@@ -107,10 +109,10 @@ body: |
107109
108110
; CHECK-LABEL: name: atomicrmw_and_i32
109111
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
110-
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
111-
; CHECK: [[CST2:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[CST]]
112-
; CHECK: [[RES:%[0-9]+]]:gpr32 = LDCLRAW [[CST2]], [[COPY]] :: (load store acquire 4 on %ir.addr)
113-
; CHECK: $w0 = COPY [[RES]]
112+
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
113+
; CHECK: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[MOVi32imm]]
114+
; CHECK: [[LDCLRAW:%[0-9]+]]:gpr32 = LDCLRAW [[ORNWrr]], [[COPY]] :: (load store acquire 4 on %ir.addr)
115+
; CHECK: $w0 = COPY [[LDCLRAW]]
114116
%0:gpr(p0) = COPY $x0
115117
%1:gpr(s32) = G_CONSTANT i32 1
116118
%2:gpr(s32) = G_ATOMICRMW_AND %0, %1 :: (load store acquire 4 on %ir.addr)
@@ -128,9 +130,9 @@ body: |
128130
129131
; CHECK-LABEL: name: atomicrmw_or_i32
130132
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
131-
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
132-
; CHECK: [[RES:%[0-9]+]]:gpr32 = LDSETLW [[CST]], [[COPY]] :: (load store release 4 on %ir.addr)
133-
; CHECK: $w0 = COPY [[RES]]
133+
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
134+
; CHECK: [[LDSETLW:%[0-9]+]]:gpr32 = LDSETLW [[MOVi32imm]], [[COPY]] :: (load store release 4 on %ir.addr)
135+
; CHECK: $w0 = COPY [[LDSETLW]]
134136
%0:gpr(p0) = COPY $x0
135137
%1:gpr(s32) = G_CONSTANT i32 1
136138
%2:gpr(s32) = G_ATOMICRMW_OR %0, %1 :: (load store release 4 on %ir.addr)
@@ -148,9 +150,9 @@ body: |
148150
149151
; CHECK-LABEL: name: atomicrmw_xor_i32
150152
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
151-
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
152-
; CHECK: [[RES:%[0-9]+]]:gpr32 = LDEORALW [[CST]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
153-
; CHECK: $w0 = COPY [[RES]]
153+
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
154+
; CHECK: [[LDEORALW:%[0-9]+]]:gpr32 = LDEORALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
155+
; CHECK: $w0 = COPY [[LDEORALW]]
154156
%0:gpr(p0) = COPY $x0
155157
%1:gpr(s32) = G_CONSTANT i32 1
156158
%2:gpr(s32) = G_ATOMICRMW_XOR %0, %1 :: (load store acq_rel 4 on %ir.addr)
@@ -168,9 +170,9 @@ body: |
168170
169171
; CHECK-LABEL: name: atomicrmw_min_i32
170172
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
171-
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
172-
; CHECK: [[RES:%[0-9]+]]:gpr32 = LDSMINALW [[CST]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
173-
; CHECK: $w0 = COPY [[RES]]
173+
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
174+
; CHECK: [[LDSMINALW:%[0-9]+]]:gpr32 = LDSMINALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
175+
; CHECK: $w0 = COPY [[LDSMINALW]]
174176
%0:gpr(p0) = COPY $x0
175177
%1:gpr(s32) = G_CONSTANT i32 1
176178
%2:gpr(s32) = G_ATOMICRMW_MIN %0, %1 :: (load store acq_rel 4 on %ir.addr)
@@ -188,9 +190,9 @@ body: |
188190
189191
; CHECK-LABEL: name: atomicrmw_max_i32
190192
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
191-
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
192-
; CHECK: [[RES:%[0-9]+]]:gpr32 = LDSMAXALW [[CST]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
193-
; CHECK: $w0 = COPY [[RES]]
193+
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
194+
; CHECK: [[LDSMAXALW:%[0-9]+]]:gpr32 = LDSMAXALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
195+
; CHECK: $w0 = COPY [[LDSMAXALW]]
194196
%0:gpr(p0) = COPY $x0
195197
%1:gpr(s32) = G_CONSTANT i32 1
196198
%2:gpr(s32) = G_ATOMICRMW_MAX %0, %1 :: (load store acq_rel 4 on %ir.addr)
@@ -208,9 +210,9 @@ body: |
208210
209211
; CHECK-LABEL: name: atomicrmw_umin_i32
210212
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
211-
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
212-
; CHECK: [[RES:%[0-9]+]]:gpr32 = LDUMINALW [[CST]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
213-
; CHECK: $w0 = COPY [[RES]]
213+
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
214+
; CHECK: [[LDUMINALW:%[0-9]+]]:gpr32 = LDUMINALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
215+
; CHECK: $w0 = COPY [[LDUMINALW]]
214216
%0:gpr(p0) = COPY $x0
215217
%1:gpr(s32) = G_CONSTANT i32 1
216218
%2:gpr(s32) = G_ATOMICRMW_UMIN %0, %1 :: (load store acq_rel 4 on %ir.addr)
@@ -228,9 +230,9 @@ body: |
228230
229231
; CHECK-LABEL: name: atomicrmw_umax_i32
230232
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
231-
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
232-
; CHECK: [[RES:%[0-9]+]]:gpr32 = LDUMAXALW [[CST]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
233-
; CHECK: $w0 = COPY [[RES]]
233+
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
234+
; CHECK: [[LDUMAXALW:%[0-9]+]]:gpr32 = LDUMAXALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
235+
; CHECK: $w0 = COPY [[LDUMAXALW]]
234236
%0:gpr(p0) = COPY $x0
235237
%1:gpr(s32) = G_CONSTANT i32 1
236238
%2:gpr(s32) = G_ATOMICRMW_UMAX %0, %1 :: (load store acq_rel 4 on %ir.addr)

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