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[GlobalISel] Check whether G_CTLZ is legal in matchUMulHToLShr (#126457)
We need to check `G_CTLZ` because the combine uses `G_CTLZ` to get log base 2, and it is not always legal for on a target. Fixes SWDEV-512440.
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‎llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5641,6 +5641,7 @@ bool CombinerHelper::matchUMulHToLShr(MachineInstr &MI) const {
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Register RHS = MI.getOperand(2).getReg();
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Register Dst = MI.getOperand(0).getReg();
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LLT Ty = MRI.getType(Dst);
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LLT RHSTy = MRI.getType(RHS);
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LLT ShiftAmtTy = getTargetLowering().getPreferredShiftAmountTy(Ty);
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auto MatchPow2ExceptOne = [&](const Constant *C) {
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if (auto *CI = dyn_cast<ConstantInt>(C))
@@ -5649,7 +5650,10 @@ bool CombinerHelper::matchUMulHToLShr(MachineInstr &MI) const {
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};
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if (!matchUnaryPredicate(MRI, RHS, MatchPow2ExceptOne, false))
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return false;
5652-
return isLegalOrBeforeLegalizer({TargetOpcode::G_LSHR, {Ty, ShiftAmtTy}});
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// We need to check both G_LSHR and G_CTLZ because the combine uses G_CTLZ to
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// get log base 2, and it is not always legal for on a target.
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return isLegalOrBeforeLegalizer({TargetOpcode::G_LSHR, {Ty, ShiftAmtTy}}) &&
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isLegalOrBeforeLegalizer({TargetOpcode::G_CTLZ, {RHSTy, RHSTy}});
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}
56545658

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void CombinerHelper::applyUMulHToLShr(MachineInstr &MI) const {

‎llvm/test/CodeGen/AMDGPU/GlobalISel/no-ctlz-from-umul-to-lshr-in-postlegalizer.ll

Lines changed: 98 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,98 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -O0 -global-isel=true %s -o - | FileCheck %s
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define void @test(ptr %p) {
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; CHECK-LABEL: test:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v2, v1
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; CHECK-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec
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; CHECK-NEXT: v_mov_b32_e32 v1, v2
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; CHECK-NEXT: s_mov_b32 s5, 16
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; CHECK-NEXT: s_mov_b32 s6, 0
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; CHECK-NEXT: v_mov_b32_e32 v2, s6
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; CHECK-NEXT: v_cvt_f32_ubyte0_e64 v2, v2
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; CHECK-NEXT: v_rcp_iflag_f32_e64 v2, v2
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; CHECK-NEXT: s_mov_b32 s4, 0x4f7ffffe
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; CHECK-NEXT: v_mov_b32_e32 v3, s4
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; CHECK-NEXT: v_mul_f32_e64 v2, v2, v3
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; CHECK-NEXT: v_cvt_u32_f32_e64 v2, v2
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; CHECK-NEXT: s_mov_b32 s7, 0
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; CHECK-NEXT: v_mov_b32_e32 v3, s7
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; CHECK-NEXT: v_mul_hi_u32 v3, v2, v3
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; CHECK-NEXT: v_add_u32_e64 v2, v2, v3
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; CHECK-NEXT: v_mov_b32_e32 v3, s5
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; CHECK-NEXT: v_mul_hi_u32 v2, v2, v3
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; CHECK-NEXT: s_mov_b32 s7, 2
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; CHECK-NEXT: v_mov_b32_e32 v3, s7
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; CHECK-NEXT: v_add_u32_e64 v2, v2, v3
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; CHECK-NEXT: v_mov_b32_e32 v3, s6
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; CHECK-NEXT: v_cvt_f32_ubyte0_e64 v3, v3
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; CHECK-NEXT: v_rcp_iflag_f32_e64 v3, v3
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; CHECK-NEXT: v_mov_b32_e32 v4, s4
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; CHECK-NEXT: v_mul_f32_e64 v3, v3, v4
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; CHECK-NEXT: v_cvt_u32_f32_e64 v3, v3
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; CHECK-NEXT: s_mov_b32 s7, 0
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; CHECK-NEXT: v_mov_b32_e32 v4, s7
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; CHECK-NEXT: v_mul_hi_u32 v4, v3, v4
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; CHECK-NEXT: v_add_u32_e64 v3, v3, v4
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; CHECK-NEXT: v_mov_b32_e32 v4, s5
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; CHECK-NEXT: v_mul_hi_u32 v3, v3, v4
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; CHECK-NEXT: s_mov_b32 s7, 2
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; CHECK-NEXT: v_mov_b32_e32 v4, s7
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; CHECK-NEXT: v_add_u32_e64 v6, v3, v4
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; CHECK-NEXT: v_mov_b32_e32 v3, s6
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; CHECK-NEXT: v_cvt_f32_ubyte0_e64 v3, v3
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; CHECK-NEXT: v_rcp_iflag_f32_e64 v3, v3
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; CHECK-NEXT: v_mov_b32_e32 v4, s4
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; CHECK-NEXT: v_mul_f32_e64 v3, v3, v4
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; CHECK-NEXT: v_cvt_u32_f32_e64 v3, v3
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; CHECK-NEXT: s_mov_b32 s7, 0
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; CHECK-NEXT: v_mov_b32_e32 v4, s7
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; CHECK-NEXT: v_mul_hi_u32 v4, v3, v4
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; CHECK-NEXT: v_add_u32_e64 v3, v3, v4
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; CHECK-NEXT: v_mov_b32_e32 v4, s5
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; CHECK-NEXT: v_mul_hi_u32 v3, v3, v4
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; CHECK-NEXT: s_mov_b32 s7, 2
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; CHECK-NEXT: v_mov_b32_e32 v4, s7
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; CHECK-NEXT: v_add_u32_e64 v3, v3, v4
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; CHECK-NEXT: v_mov_b32_e32 v4, s6
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; CHECK-NEXT: v_cvt_f32_ubyte0_e64 v4, v4
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; CHECK-NEXT: v_rcp_iflag_f32_e64 v4, v4
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; CHECK-NEXT: v_mov_b32_e32 v5, s4
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; CHECK-NEXT: v_mul_f32_e64 v4, v4, v5
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; CHECK-NEXT: v_cvt_u32_f32_e64 v4, v4
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; CHECK-NEXT: s_mov_b32 s4, 0
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; CHECK-NEXT: v_mov_b32_e32 v5, s4
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; CHECK-NEXT: v_mul_hi_u32 v5, v4, v5
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; CHECK-NEXT: v_add_u32_e64 v4, v4, v5
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; CHECK-NEXT: v_mov_b32_e32 v5, s5
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; CHECK-NEXT: v_mul_hi_u32 v4, v4, v5
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; CHECK-NEXT: s_mov_b32 s4, 2
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; CHECK-NEXT: v_mov_b32_e32 v5, s4
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; CHECK-NEXT: v_add_u32_e64 v4, v4, v5
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; CHECK-NEXT: s_mov_b32 s4, 0xff
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; CHECK-NEXT: v_mov_b32_e32 v5, s4
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; CHECK-NEXT: v_mov_b32_e32 v7, s4
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; CHECK-NEXT: v_and_b32_e64 v7, v6, v7
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; CHECK-NEXT: s_mov_b32 s6, 8
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; CHECK-NEXT: v_mov_b32_e32 v6, s6
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; CHECK-NEXT: v_lshlrev_b32_e64 v6, v6, v7
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; CHECK-NEXT: v_and_or_b32 v2, v2, v5, v6
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; CHECK-NEXT: v_mov_b32_e32 v5, s4
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; CHECK-NEXT: v_and_b32_e64 v5, v3, v5
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; CHECK-NEXT: v_mov_b32_e32 v3, s5
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; CHECK-NEXT: v_lshlrev_b32_e64 v3, v3, v5
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; CHECK-NEXT: v_mov_b32_e32 v5, s4
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; CHECK-NEXT: v_and_b32_e64 v5, v4, v5
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; CHECK-NEXT: s_mov_b32 s4, 24
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; CHECK-NEXT: v_mov_b32_e32 v4, s4
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; CHECK-NEXT: v_lshlrev_b32_e64 v4, v4, v5
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; CHECK-NEXT: v_or3_b32 v2, v2, v3, v4
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; CHECK-NEXT: flat_store_dword v[0:1], v2
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; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
95+
%B = udiv <4 x i8> splat (i8 16), zeroinitializer
96+
store <4 x i8> %B, ptr %p, align 4
97+
ret void
98+
}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/no-ctlz-from-umul-to-lshr-in-postlegalizer.mir

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,23 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2+
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=amdgpu-postlegalizer-combiner %s -o - | FileCheck %s
3+
4+
---
5+
name: test
6+
tracksRegLiveness: true
7+
legalized: true
8+
body: |
9+
bb.0:
10+
liveins: $vgpr0, $vgpr1
11+
; CHECK-LABEL: name: test
12+
; CHECK: liveins: $vgpr0, $vgpr1
13+
; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY]], [[C]]
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; CHECK-NEXT: $vgpr0 = COPY [[UMULH]](s32)
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; CHECK-NEXT: SI_RETURN implicit $vgpr0
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = G_CONSTANT i32 4
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%2:_(s32) = G_UMULH %0:_, %1:_
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$vgpr0 = COPY %2:_(s32)
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SI_RETURN implicit $vgpr0

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