handle review comments

Author: ergawy

mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp

@@ -29,6 +29,7 @@
 #include "llvm/ADT/TypeSwitch.h"
 #include "llvm/Frontend/OpenMP/OMPConstants.h"
 #include "llvm/Frontend/OpenMP/OMPIRBuilder.h"
+#include "llvm/IR/Constants.h"
 #include "llvm/IR/DebugInfoMetadata.h"
 #include "llvm/IR/DerivedTypes.h"
 #include "llvm/IR/IRBuilder.h"
@@ -5336,9 +5337,9 @@ convertTargetOpsInNest(Operation *op, llvm::IRBuilderBase &builder,
               assert(builder.GetInsertBlock() &&
                      "No insert block is set for the builder");
               for (auto iv : loopNest.getIVs()) {
-                // Create fake allocas just to maintain IR validity.
+                // Map iv to an undefined value just to keep the IR validity.
                 moduleTranslation.mapValue(
-                    iv, builder.CreateAlloca(
+                    iv, llvm::PoisonValue::get(
                             moduleTranslation.convertType(iv.getType())));
               }
             }

mlir/test/Target/LLVMIR/openmp-target-nesting-in-host-ops.mlir

@@ -51,10 +51,9 @@ module attributes {llvm.target_triple = "amdgcn-amd-amdhsa", omp.is_gpu = true,
 // CHECK-NEXT:    %{{.*}} = alloca i32, i64 1, align 4
 // CHECK-NEXT:    br label %omp.wsloop.fake.region
 // CHECK:       omp.wsloop.fake.region:
-// CHECK-NEXT:    %{{.*}} = alloca i32, align 4
 // CHECK-NEXT:    br label %omp.loop_nest.fake.region
 // CHECK:       omp.loop_nest.fake.region:
-// CHECK-NEXT:    store ptr %3, ptr %2, align 8
+// CHECK-NEXT:    store i32 poison, ptr %{{.*}}
 // CHECK-NEXT:    br label %omp.region.cont1
 // CHECK:       omp.region.cont1:
 // CHECK-NEXT:    br label %omp.region.cont