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[LoongArch] Custom legalize i32 operations for LA64 to reduce signed extensions (#93811)
1 parent e12bf36 commit 718331f

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11 files changed

+63
-34
lines changed

11 files changed

+63
-34
lines changed

‎llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -121,6 +121,8 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
121121
// Set operations for LA64 only.
122122

123123
if (Subtarget.is64Bit()) {
124+
setOperationAction(ISD::ADD, MVT::i32, Custom);
125+
setOperationAction(ISD::SUB, MVT::i32, Custom);
124126
setOperationAction(ISD::SHL, MVT::i32, Custom);
125127
setOperationAction(ISD::SRA, MVT::i32, Custom);
126128
setOperationAction(ISD::SRL, MVT::i32, Custom);
@@ -1723,6 +1725,18 @@ static SDValue customLegalizeToWOp(SDNode *N, SelectionDAG &DAG, int NumOp,
17231725
return DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), NewRes);
17241726
}
17251727

1728+
// Converts the given 32-bit operation to a i64 operation with signed extension
1729+
// semantic to reduce the signed extension instructions.
1730+
static SDValue customLegalizeToWOpWithSExt(SDNode *N, SelectionDAG &DAG) {
1731+
SDLoc DL(N);
1732+
SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0));
1733+
SDValue NewOp1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
1734+
SDValue NewWOp = DAG.getNode(N->getOpcode(), DL, MVT::i64, NewOp0, NewOp1);
1735+
SDValue NewRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i64, NewWOp,
1736+
DAG.getValueType(MVT::i32));
1737+
return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, NewRes);
1738+
}
1739+
17261740
// Helper function that emits error message for intrinsics with/without chain
17271741
// and return a UNDEF or and the chain as the results.
17281742
static void emitErrorAndReplaceIntrinsicResults(
@@ -1846,6 +1860,12 @@ void LoongArchTargetLowering::ReplaceNodeResults(
18461860
switch (N->getOpcode()) {
18471861
default:
18481862
llvm_unreachable("Don't know how to legalize this operation");
1863+
case ISD::ADD:
1864+
case ISD::SUB:
1865+
assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
1866+
"Unexpected custom legalisation");
1867+
Results.push_back(customLegalizeToWOpWithSExt(N, DAG));
1868+
break;
18491869
case ISD::UDIV:
18501870
case ISD::UREM:
18511871
assert(VT == MVT::i32 && Subtarget.is64Bit() &&

‎llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -441,7 +441,7 @@ def simm16_lsl16 : Operand<GRLenVT>,
441441
// A 32-bit signed immediate expressible with a pair of `addu16i.d + addi` for
442442
// use in additions.
443443
def simm32_hi16_lo12: Operand<GRLenVT>, ImmLeaf<GRLenVT, [{
444-
return isShiftedInt<16, 16>(Imm - SignExtend64<12>(Imm));
444+
return !isInt<12>(Imm) && isShiftedInt<16, 16>(Imm - SignExtend64<12>(Imm));
445445
}]>;
446446

447447
def BareSymbol : AsmOperandClass {
@@ -1106,11 +1106,8 @@ foreach Idx = 1...3 in {
11061106

11071107
let Predicates = [IsLA64] in {
11081108
def : PatGprGpr<add, ADD_D>;
1109-
def : PatGprGpr_32<add, ADD_W>;
11101109
def : PatGprImm<add, ADDI_D, simm12>;
1111-
def : PatGprImm_32<add, ADDI_W, simm12>;
11121110
def : PatGprGpr<sub, SUB_D>;
1113-
def : PatGprGpr_32<sub, SUB_W>;
11141111
def : PatGprGpr<sdiv, DIV_D>;
11151112
def : PatGprGpr_32<sdiv, DIV_W>;
11161113
def : PatGprGpr<udiv, DIV_DU>;

‎llvm/test/CodeGen/LoongArch/alsl.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@ define i32 @alsl_i32(i32 signext %a, i32 signext %b) nounwind {
4242
;
4343
; LA64-LABEL: alsl_i32:
4444
; LA64: # %bb.0: # %entry
45-
; LA64-NEXT: alsl.d $a0, $a0, $a1, 3
45+
; LA64-NEXT: alsl.w $a0, $a0, $a1, 3
4646
; LA64-NEXT: ret
4747
entry:
4848
%mul = mul nsw i32 %a, 8
@@ -178,7 +178,7 @@ define i32 @mul_add_i32(i32 signext %a, i32 signext %b) nounwind {
178178
; LA64: # %bb.0: # %entry
179179
; LA64-NEXT: slli.d $a2, $a0, 3
180180
; LA64-NEXT: alsl.d $a0, $a0, $a2, 2
181-
; LA64-NEXT: add.d $a0, $a1, $a0
181+
; LA64-NEXT: add.w $a0, $a1, $a0
182182
; LA64-NEXT: ret
183183
entry:
184184
%mul = mul nsw i32 %a, 12
@@ -325,7 +325,7 @@ define i32 @alsl_neg_i32(i32 signext %a, i32 signext %b) nounwind {
325325
; LA64-LABEL: alsl_neg_i32:
326326
; LA64: # %bb.0: # %entry
327327
; LA64-NEXT: alsl.d $a0, $a0, $a0, 3
328-
; LA64-NEXT: sub.d $a0, $a1, $a0
328+
; LA64-NEXT: sub.w $a0, $a1, $a0
329329
; LA64-NEXT: ret
330330
entry:
331331
%mul = mul nsw i32 %a, -9

‎llvm/test/CodeGen/LoongArch/atomicrmw-uinc-udec-wrap.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,7 @@ define i32 @atomicrmw_uinc_wrap_i32(ptr %ptr, i32 %val) {
112112
; LA64-NEXT: # =>This Loop Header: Depth=1
113113
; LA64-NEXT: # Child Loop BB2_3 Depth 2
114114
; LA64-NEXT: move $a3, $a2
115-
; LA64-NEXT: addi.d $a2, $a2, 1
115+
; LA64-NEXT: addi.w $a2, $a2, 1
116116
; LA64-NEXT: sltu $a4, $a3, $a1
117117
; LA64-NEXT: xori $a4, $a4, 1
118118
; LA64-NEXT: masknez $a4, $a2, $a4
@@ -298,7 +298,7 @@ define i32 @atomicrmw_udec_wrap_i32(ptr %ptr, i32 %val) {
298298
; LA64-NEXT: # =>This Loop Header: Depth=1
299299
; LA64-NEXT: # Child Loop BB6_3 Depth 2
300300
; LA64-NEXT: move $a4, $a2
301-
; LA64-NEXT: addi.d $a2, $a2, -1
301+
; LA64-NEXT: addi.w $a2, $a2, -1
302302
; LA64-NEXT: sltui $a5, $a4, 1
303303
; LA64-NEXT: sltu $a6, $a3, $a4
304304
; LA64-NEXT: masknez $a2, $a2, $a6

‎llvm/test/CodeGen/LoongArch/ir-instruction/add.ll

Lines changed: 11 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ define i32 @add_i32(i32 %x, i32 %y) {
5454
;
5555
; LA64-LABEL: add_i32:
5656
; LA64: # %bb.0:
57-
; LA64-NEXT: add.d $a0, $a0, $a1
57+
; LA64-NEXT: add.w $a0, $a0, $a1
5858
; LA64-NEXT: ret
5959
%add = add i32 %x, %y
6060
ret i32 %add
@@ -144,7 +144,7 @@ define i32 @add_i32_3(i32 %x) {
144144
;
145145
; LA64-LABEL: add_i32_3:
146146
; LA64: # %bb.0:
147-
; LA64-NEXT: addi.d $a0, $a0, 3
147+
; LA64-NEXT: addi.w $a0, $a0, 3
148148
; LA64-NEXT: ret
149149
%add = add i32 %x, 3
150150
ret i32 %add
@@ -195,6 +195,7 @@ define i32 @add_i32_0x12340000(i32 %x) {
195195
; LA64-LABEL: add_i32_0x12340000:
196196
; LA64: # %bb.0:
197197
; LA64-NEXT: addu16i.d $a0, $a0, 4660
198+
; LA64-NEXT: addi.w $a0, $a0, 0
198199
; LA64-NEXT: ret
199200
%add = add i32 %x, 305397760
200201
ret i32 %add
@@ -244,6 +245,7 @@ define i32 @add_i32_0x7fff0000(i32 %x) {
244245
; LA64-LABEL: add_i32_0x7fff0000:
245246
; LA64: # %bb.0:
246247
; LA64-NEXT: addu16i.d $a0, $a0, 32767
248+
; LA64-NEXT: addi.w $a0, $a0, 0
247249
; LA64-NEXT: ret
248250
%add = add i32 %x, 2147418112
249251
ret i32 %add
@@ -293,6 +295,7 @@ define i32 @add_i32_minus_0x80000000(i32 %x) {
293295
; LA64-LABEL: add_i32_minus_0x80000000:
294296
; LA64: # %bb.0:
295297
; LA64-NEXT: addu16i.d $a0, $a0, -32768
298+
; LA64-NEXT: addi.w $a0, $a0, 0
296299
; LA64-NEXT: ret
297300
%add = add i32 %x, -2147483648
298301
ret i32 %add
@@ -343,6 +346,7 @@ define i32 @add_i32_minus_0x10000(i32 %x) {
343346
; LA64-LABEL: add_i32_minus_0x10000:
344347
; LA64: # %bb.0:
345348
; LA64-NEXT: addu16i.d $a0, $a0, -1
349+
; LA64-NEXT: addi.w $a0, $a0, 0
346350
; LA64-NEXT: ret
347351
%add = add i32 %x, -65536
348352
ret i32 %add
@@ -396,7 +400,7 @@ define i32 @add_i32_0x7fff07ff(i32 %x) {
396400
; LA64-LABEL: add_i32_0x7fff07ff:
397401
; LA64: # %bb.0:
398402
; LA64-NEXT: addu16i.d $a0, $a0, 32767
399-
; LA64-NEXT: addi.d $a0, $a0, 2047
403+
; LA64-NEXT: addi.w $a0, $a0, 2047
400404
; LA64-NEXT: ret
401405
%add = add i32 %x, 2147420159
402406
ret i32 %add
@@ -450,7 +454,7 @@ define i32 @add_i32_0x7ffef800(i32 %x) {
450454
; LA64-LABEL: add_i32_0x7ffef800:
451455
; LA64: # %bb.0:
452456
; LA64-NEXT: addu16i.d $a0, $a0, 32767
453-
; LA64-NEXT: addi.d $a0, $a0, -2048
457+
; LA64-NEXT: addi.w $a0, $a0, -2048
454458
; LA64-NEXT: ret
455459
%add = add i32 %x, 2147416064
456460
ret i32 %add
@@ -525,7 +529,7 @@ define i32 @add_i32_minus_0x23450679(i32 %x) {
525529
; LA64-LABEL: add_i32_minus_0x23450679:
526530
; LA64: # %bb.0:
527531
; LA64-NEXT: addu16i.d $a0, $a0, -9029
528-
; LA64-NEXT: addi.d $a0, $a0, -1657
532+
; LA64-NEXT: addi.w $a0, $a0, -1657
529533
; LA64-NEXT: ret
530534
%add = add i32 %x, -591726201
531535
ret i32 %add
@@ -580,7 +584,7 @@ define i32 @add_i32_minus_0x2345fedd(i32 %x) {
580584
; LA64-LABEL: add_i32_minus_0x2345fedd:
581585
; LA64: # %bb.0:
582586
; LA64-NEXT: addu16i.d $a0, $a0, -9030
583-
; LA64-NEXT: addi.d $a0, $a0, 291
587+
; LA64-NEXT: addi.w $a0, $a0, 291
584588
; LA64-NEXT: ret
585589
%add = add i32 %x, -591789789
586590
ret i32 %add
@@ -680,7 +684,7 @@ define i32 @add_i32_minus_0x80000800(i32 %x) {
680684
; LA64: # %bb.0:
681685
; LA64-NEXT: lu12i.w $a1, 524287
682686
; LA64-NEXT: ori $a1, $a1, 2048
683-
; LA64-NEXT: add.d $a0, $a0, $a1
687+
; LA64-NEXT: add.w $a0, $a0, $a1
684688
; LA64-NEXT: ret
685689
%add = add i32 %x, -2147485696
686690
ret i32 %add

‎llvm/test/CodeGen/LoongArch/ir-instruction/and.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -444,7 +444,7 @@ define i32 @and_add_lsr(i32 %x, i32 %y) {
444444
;
445445
; LA64-LABEL: and_add_lsr:
446446
; LA64: # %bb.0:
447-
; LA64-NEXT: addi.d $a0, $a0, -1
447+
; LA64-NEXT: addi.w $a0, $a0, -1
448448
; LA64-NEXT: bstrpick.d $a1, $a1, 31, 20
449449
; LA64-NEXT: and $a0, $a1, $a0
450450
; LA64-NEXT: ret

‎llvm/test/CodeGen/LoongArch/ir-instruction/call.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@ define i32 @defined_function(i32 %a) nounwind {
3434
;
3535
; LA64-LABEL: defined_function:
3636
; LA64: # %bb.0:
37-
; LA64-NEXT: addi.d $a0, $a0, 1
37+
; LA64-NEXT: addi.w $a0, $a0, 1
3838
; LA64-NEXT: ret
3939
%1 = add i32 %a, 1
4040
ret i32 %1

‎llvm/test/CodeGen/LoongArch/ir-instruction/load-store.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ define i32 @load_store_global() nounwind {
3232
; LA64NOPIC-NEXT: pcalau12i $a0, %pc_hi20(G)
3333
; LA64NOPIC-NEXT: addi.d $a1, $a0, %pc_lo12(G)
3434
; LA64NOPIC-NEXT: ld.w $a0, $a1, 0
35-
; LA64NOPIC-NEXT: addi.d $a0, $a0, 1
35+
; LA64NOPIC-NEXT: addi.w $a0, $a0, 1
3636
; LA64NOPIC-NEXT: st.w $a0, $a1, 0
3737
; LA64NOPIC-NEXT: ret
3838
;
@@ -41,7 +41,7 @@ define i32 @load_store_global() nounwind {
4141
; LA64PIC-NEXT: pcalau12i $a0, %pc_hi20(.LG$local)
4242
; LA64PIC-NEXT: addi.d $a1, $a0, %pc_lo12(.LG$local)
4343
; LA64PIC-NEXT: ld.w $a0, $a1, 0
44-
; LA64PIC-NEXT: addi.d $a0, $a0, 1
44+
; LA64PIC-NEXT: addi.w $a0, $a0, 1
4545
; LA64PIC-NEXT: st.w $a0, $a1, 0
4646
; LA64PIC-NEXT: ret
4747
%v = load i32, ptr @G

‎llvm/test/CodeGen/LoongArch/ir-instruction/sub.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ define i32 @sub_i32(i32 %x, i32 %y) {
5454
;
5555
; LA64-LABEL: sub_i32:
5656
; LA64: # %bb.0:
57-
; LA64-NEXT: sub.d $a0, $a0, $a1
57+
; LA64-NEXT: sub.w $a0, $a0, $a1
5858
; LA64-NEXT: ret
5959
%sub = sub i32 %x, %y
6060
ret i32 %sub

‎llvm/test/CodeGen/LoongArch/select-to-shiftand.ll

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -198,10 +198,9 @@ define i32 @sub_clamp_zero_i32(i32 signext %x, i32 signext %y) {
198198
;
199199
; LA64-LABEL: sub_clamp_zero_i32:
200200
; LA64: # %bb.0:
201-
; LA64-NEXT: sub.d $a2, $a0, $a1
202201
; LA64-NEXT: sub.w $a0, $a0, $a1
203-
; LA64-NEXT: srai.d $a0, $a0, 31
204-
; LA64-NEXT: andn $a0, $a2, $a0
202+
; LA64-NEXT: srai.d $a1, $a0, 31
203+
; LA64-NEXT: andn $a0, $a0, $a1
205204
; LA64-NEXT: ret
206205
%sub = sub nsw i32 %x, %y
207206
%cmp = icmp sgt i32 %sub, 0

‎llvm/test/CodeGen/LoongArch/sextw-removal.ll

Lines changed: 19 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -793,7 +793,9 @@ define signext i32 @test14(i32 signext %0, i32 signext %1) {
793793
; NORMV-NEXT: blt $a4, $a5, .LBB13_5
794794
; NORMV-NEXT: # %bb.3: # in Loop: Header=BB13_2 Depth=1
795795
; NORMV-NEXT: add.d $a0, $a3, $a0
796-
; NORMV-NEXT: addi.w $a3, $a3, 1
796+
; NORMV-NEXT: addi.d $a3, $a3, 1
797+
; NORMV-NEXT: addi.w $a3, $a3, 0
798+
; NORMV-NEXT: addi.d $a0, $a0, 0
797799
; NORMV-NEXT: blt $a3, $a1, .LBB13_2
798800
; NORMV-NEXT: .LBB13_4:
799801
; NORMV-NEXT: addi.w $a0, $a0, 0
@@ -861,7 +863,9 @@ define signext i32 @test14b(i32 %0, i32 signext %1) {
861863
; NORMV-NEXT: blt $a4, $a5, .LBB14_5
862864
; NORMV-NEXT: # %bb.3: # in Loop: Header=BB14_2 Depth=1
863865
; NORMV-NEXT: add.d $a0, $a3, $a0
864-
; NORMV-NEXT: addi.w $a3, $a3, 1
866+
; NORMV-NEXT: addi.d $a3, $a3, 1
867+
; NORMV-NEXT: addi.w $a3, $a3, 0
868+
; NORMV-NEXT: addi.d $a0, $a0, 0
865869
; NORMV-NEXT: blt $a3, $a1, .LBB14_2
866870
; NORMV-NEXT: .LBB14_4:
867871
; NORMV-NEXT: addi.w $a0, $a0, 0
@@ -929,7 +933,9 @@ define signext i32 @test14c(i32 zeroext %0, i32 signext %1) {
929933
; NORMV-NEXT: blt $a4, $a5, .LBB15_5
930934
; NORMV-NEXT: # %bb.3: # in Loop: Header=BB15_2 Depth=1
931935
; NORMV-NEXT: add.d $a0, $a3, $a0
932-
; NORMV-NEXT: addi.w $a3, $a3, 1
936+
; NORMV-NEXT: addi.d $a3, $a3, 1
937+
; NORMV-NEXT: addi.w $a3, $a3, 0
938+
; NORMV-NEXT: addi.d $a0, $a0, 0
933939
; NORMV-NEXT: blt $a3, $a1, .LBB15_2
934940
; NORMV-NEXT: .LBB15_4:
935941
; NORMV-NEXT: addi.w $a0, $a0, 0
@@ -996,7 +1002,9 @@ define signext i32 @test14d(i31 zeroext %0, i32 signext %1) {
9961002
; NORMV-NEXT: blt $a4, $a5, .LBB16_5
9971003
; NORMV-NEXT: # %bb.3: # in Loop: Header=BB16_2 Depth=1
9981004
; NORMV-NEXT: add.d $a0, $a3, $a0
999-
; NORMV-NEXT: addi.w $a3, $a3, 1
1005+
; NORMV-NEXT: addi.d $a3, $a3, 1
1006+
; NORMV-NEXT: addi.w $a3, $a3, 0
1007+
; NORMV-NEXT: addi.d $a0, $a0, 0
10001008
; NORMV-NEXT: blt $a3, $a1, .LBB16_2
10011009
; NORMV-NEXT: .LBB16_4:
10021010
; NORMV-NEXT: addi.w $a0, $a0, 0
@@ -1122,8 +1130,8 @@ define signext i32 @bug(i32 signext %x) {
11221130
; CHECK-NEXT: masknez $a1, $a1, $a2
11231131
; CHECK-NEXT: maskeqz $a2, $a4, $a2
11241132
; CHECK-NEXT: or $a1, $a2, $a1
1125-
; CHECK-NEXT: srai.d $a0, $a0, 31
11261133
; CHECK-NEXT: nor $a0, $a0, $zero
1134+
; CHECK-NEXT: srli.d $a0, $a0, 31
11271135
; CHECK-NEXT: add.w $a0, $a1, $a0
11281136
; CHECK-NEXT: ret
11291137
; CHECK-NEXT: .LBB18_2:
@@ -1176,13 +1184,13 @@ define signext i32 @bug(i32 signext %x) {
11761184
; NORMV-NEXT: masknez $a1, $a1, $a2
11771185
; NORMV-NEXT: maskeqz $a2, $a4, $a2
11781186
; NORMV-NEXT: or $a1, $a2, $a1
1179-
; NORMV-NEXT: srai.d $a0, $a0, 31
11801187
; NORMV-NEXT: nor $a0, $a0, $zero
1188+
; NORMV-NEXT: srli.d $a0, $a0, 31
11811189
; NORMV-NEXT: add.d $a0, $a1, $a0
11821190
; NORMV-NEXT: addi.w $a0, $a0, 0
11831191
; NORMV-NEXT: ret
11841192
; NORMV-NEXT: .LBB18_2:
1185-
; NORMV-NEXT: addi.w $a0, $zero, 0
1193+
; NORMV-NEXT: move $a0, $zero
11861194
; NORMV-NEXT: ret
11871195
entry:
11881196
%tobool.not = icmp eq i32 %x, 0
@@ -1345,7 +1353,7 @@ declare zeroext i16 @bat(i32 signext)
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define signext i32 @sextw_sh2add(i1 zeroext %0, ptr %1, i32 signext %2, i32 signext %3, i32 signext %4) {
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; CHECK-LABEL: sextw_sh2add:
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; CHECK: # %bb.0:
1348-
; CHECK-NEXT: alsl.d $a2, $a2, $a3, 2
1356+
; CHECK-NEXT: alsl.w $a2, $a2, $a3, 2
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; CHECK-NEXT: beqz $a0, .LBB21_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: st.w $a2, $a1, 0
@@ -1355,12 +1363,13 @@ define signext i32 @sextw_sh2add(i1 zeroext %0, ptr %1, i32 signext %2, i32 sign
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;
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; NORMV-LABEL: sextw_sh2add:
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; NORMV: # %bb.0:
1358-
; NORMV-NEXT: alsl.d $a2, $a2, $a3, 2
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; NORMV-NEXT: alsl.w $a2, $a2, $a3, 2
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; NORMV-NEXT: beqz $a0, .LBB21_2
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; NORMV-NEXT: # %bb.1:
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; NORMV-NEXT: st.w $a2, $a1, 0
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; NORMV-NEXT: .LBB21_2:
1363-
; NORMV-NEXT: add.w $a0, $a2, $a4
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; NORMV-NEXT: add.d $a0, $a2, $a4
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; NORMV-NEXT: addi.w $a0, $a0, 0
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; NORMV-NEXT: ret
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%6 = shl i32 %2, 2
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%7 = add i32 %6, %3

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