[ConstantHoisting] Add a TTI hook to prevent hoisting.

Code generation can sometimes simplify expensive operations when
an operand is constant.  An example of this is divides on AArch64
where they can be rewritten using a cheaper sequence of multiplies
and subtracts.  Doing this is often better than hoisting expensive
constants which are likely to be hoisted by MachineLICM anyway.

Author: paulwalker-arm

llvm/include/llvm/Analysis/TargetTransformInfo.h

@@ -986,6 +986,18 @@ class TargetTransformInfo {
   /// more beneficial constant hoisting is).
   InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx,
                                         const APInt &Imm, Type *Ty) const;
+
+  /// Returns false if the target prefers to keep an instruction's constant
+  /// operands attached. It is not required for this function to perform
+  /// detailed constant analysis and in fact returning true does not imply
+  /// the instruction has any constant operands. This hook exists soley to
+  /// disable constant hoisting for reasons beyond the cost of generating a
+  /// constant. The motivating example is divides whereby hoisting constants
+  /// prevents the code generator's ability to transform them into combinations
+  /// of simpler operations.
+  bool isCandidateForConstantHoisting(const Instruction &Inst,
+                                      const Function &Fn) const;
+
   /// @}
 
   /// \name Vector Target Information
@@ -1847,6 +1859,8 @@ class TargetTransformInfo::Concept {
   virtual InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
                                               const APInt &Imm, Type *Ty,
                                               TargetCostKind CostKind) = 0;
+  virtual bool isCandidateForConstantHoisting(const Instruction &Inst,
+                                              const Function &Fn) const = 0;
   virtual unsigned getNumberOfRegisters(unsigned ClassID) const = 0;
   virtual unsigned getRegisterClassForType(bool Vector,
                                            Type *Ty = nullptr) const = 0;
@@ -2399,6 +2413,10 @@ class TargetTransformInfo::Model final : public TargetTransformInfo::Concept {
                                       TargetCostKind CostKind) override {
     return Impl.getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind);
   }
+  bool isCandidateForConstantHoisting(const Instruction &Inst,
+                                      const Function &Fn) const override {
+    return Impl.isCandidateForConstantHoisting(Inst, Fn);
+  }
   unsigned getNumberOfRegisters(unsigned ClassID) const override {
     return Impl.getNumberOfRegisters(ClassID);
   }

llvm/include/llvm/Analysis/TargetTransformInfoImpl.h

@@ -425,6 +425,11 @@ class TargetTransformInfoImplBase {
     return TTI::TCC_Free;
   }
 
+  bool isCandidateForConstantHoisting(const Instruction &Inst,
+                                      const Function &Fn) const {
+    return true;
+  }
+
   unsigned getNumberOfRegisters(unsigned ClassID) const { return 8; }
 
   unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const {

llvm/lib/Analysis/TargetTransformInfo.cpp

@@ -678,6 +678,11 @@ TargetTransformInfo::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
   return Cost;
 }
 
+bool TargetTransformInfo::isCandidateForConstantHoisting(
+    const Instruction &Inst, const Function &Fn) const {
+  return TTIImpl->isCandidateForConstantHoisting(Inst, Fn);
+}
+
 unsigned TargetTransformInfo::getNumberOfRegisters(unsigned ClassID) const {
   return TTIImpl->getNumberOfRegisters(ClassID);
 }

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

@@ -382,6 +382,25 @@ AArch64TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
   return AArch64TTIImpl::getIntImmCost(Imm, Ty, CostKind);
 }
 
+bool AArch64TTIImpl::isCandidateForConstantHoisting(const Instruction &Inst,
+                                                    const Function &Fn) const {
+  switch (Inst.getOpcode()) {
+  default:
+    break;
+  case Instruction::SDiv:
+  case Instruction::SRem:
+  case Instruction::UDiv:
+  case Instruction::URem: {
+    if (!isa<ConstantInt>(Inst.getOperand(1)))
+      return true;
+    EVT VT = TLI->getValueType(DL, Inst.getType());
+    return TLI->isIntDivCheap(VT, Fn.getAttributes());
+  }
+  };
+
+  return true;
+}
+
 TargetTransformInfo::PopcntSupportKind
 AArch64TTIImpl::getPopcntSupport(unsigned TyWidth) {
   assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h

@@ -91,6 +91,10 @@ class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> {
   InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
                                       const APInt &Imm, Type *Ty,
                                       TTI::TargetCostKind CostKind);
+
+  bool isCandidateForConstantHoisting(const Instruction &Inst,
+                                      const Function &Fn) const;
+
   TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
 
   /// @}

llvm/lib/Transforms/Scalar/ConstantHoisting.cpp

@@ -523,7 +523,9 @@ void ConstantHoistingPass::collectConstantCandidates(Function &Fn) {
     if (!DT->isReachableFromEntry(&BB))
       continue;
     for (Instruction &Inst : BB)
-      collectConstantCandidates(ConstCandMap, &Inst);
+      // Skip instructions the target prefers constants remain attached.
+      if (TTI->isCandidateForConstantHoisting(Inst, Fn))
+        collectConstantCandidates(ConstCandMap, &Inst);
   }
 }
 

llvm/test/Transforms/ConstantHoisting/AArch64/large-immediate.ll

@@ -44,9 +44,8 @@ define i512 @test3(i512 %a) {
 define i64 @sdiv(i64 %a) {
 ; CHECK-LABEL: define i64 @sdiv(
 ; CHECK-SAME: i64 [[A:%.*]]) {
-; CHECK-NEXT:    [[CONST:%.*]] = bitcast i64 4294967087 to i64
-; CHECK-NEXT:    [[TMP1:%.*]] = sdiv i64 [[A]], [[CONST]]
-; CHECK-NEXT:    [[TMP2:%.*]] = add i64 [[TMP1]], [[CONST]]
+; CHECK-NEXT:    [[TMP1:%.*]] = sdiv i64 [[A]], 4294967087
+; CHECK-NEXT:    [[TMP2:%.*]] = add i64 [[TMP1]], 4294967087
 ; CHECK-NEXT:    ret i64 [[TMP2]]
 ;
   %1 = sdiv i64 %a, 4294967087
@@ -58,9 +57,8 @@ define i64 @sdiv(i64 %a) {
 define i64 @srem(i64 %a) {
 ; CHECK-LABEL: define i64 @srem(
 ; CHECK-SAME: i64 [[A:%.*]]) {
-; CHECK-NEXT:    [[CONST:%.*]] = bitcast i64 4294967087 to i64
-; CHECK-NEXT:    [[TMP1:%.*]] = srem i64 [[A]], [[CONST]]
-; CHECK-NEXT:    [[TMP2:%.*]] = add i64 [[TMP1]], [[CONST]]
+; CHECK-NEXT:    [[TMP1:%.*]] = srem i64 [[A]], 4294967087
+; CHECK-NEXT:    [[TMP2:%.*]] = add i64 [[TMP1]], 4294967087
 ; CHECK-NEXT:    ret i64 [[TMP2]]
 ;
   %1 = srem i64 %a, 4294967087
@@ -72,9 +70,8 @@ define i64 @srem(i64 %a) {
 define i64 @udiv(i64 %a) {
 ; CHECK-LABEL: define i64 @udiv(
 ; CHECK-SAME: i64 [[A:%.*]]) {
-; CHECK-NEXT:    [[CONST:%.*]] = bitcast i64 4294967087 to i64
-; CHECK-NEXT:    [[TMP1:%.*]] = udiv i64 [[A]], [[CONST]]
-; CHECK-NEXT:    [[TMP2:%.*]] = add i64 [[TMP1]], [[CONST]]
+; CHECK-NEXT:    [[TMP1:%.*]] = udiv i64 [[A]], 4294967087
+; CHECK-NEXT:    [[TMP2:%.*]] = add i64 [[TMP1]], 4294967087
 ; CHECK-NEXT:    ret i64 [[TMP2]]
 ;
   %1 = udiv i64 %a, 4294967087
@@ -86,9 +83,8 @@ define i64 @udiv(i64 %a) {
 define i64 @urem(i64 %a) {
 ; CHECK-LABEL: define i64 @urem(
 ; CHECK-SAME: i64 [[A:%.*]]) {
-; CHECK-NEXT:    [[CONST:%.*]] = bitcast i64 4294967087 to i64
-; CHECK-NEXT:    [[TMP1:%.*]] = urem i64 [[A]], [[CONST]]
-; CHECK-NEXT:    [[TMP2:%.*]] = add i64 [[TMP1]], [[CONST]]
+; CHECK-NEXT:    [[TMP1:%.*]] = urem i64 [[A]], 4294967087
+; CHECK-NEXT:    [[TMP2:%.*]] = add i64 [[TMP1]], 4294967087
 ; CHECK-NEXT:    ret i64 [[TMP2]]
 ;
   %1 = urem i64 %a, 4294967087