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[RISCV][llvm-exegesis] Add unittests. NFC (#121862)
This is largely based on Mips and PowerPC.
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‎llvm/unittests/tools/llvm-exegesis/CMakeLists.txt

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if(LLVM_TARGETS_TO_BUILD MATCHES "Mips")
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include(Mips/CMakeLists.txt)
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endif()
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if(LLVM_TARGETS_TO_BUILD MATCHES "RISCV")
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include(RISCV/CMakeLists.txt)
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endif()
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include_directories(${exegesis_includes})
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‎llvm/unittests/tools/llvm-exegesis/RISCV/CMakeLists.txt

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add_llvm_exegesis_unittest_includes(
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${LLVM_MAIN_SRC_DIR}/lib/Target/RISCV
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${LLVM_BINARY_DIR}/lib/Target/RISCV
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${LLVM_MAIN_SRC_DIR}/tools/llvm-exegesis/lib
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)
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add_llvm_exegesis_unittest_link_components(
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MC
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MCParser
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Object
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Support
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Symbolize
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RISCV
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)
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add_llvm_exegesis_unittest_sources(
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SnippetGeneratorTest.cpp
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TargetTest.cpp
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)
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add_llvm_exegesis_unittest_link_libraries(
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LLVMExegesisRISCV)

‎llvm/unittests/tools/llvm-exegesis/RISCV/SnippetGeneratorTest.cpp

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//===-- SnippetGeneratorTest.cpp --------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "../Common/AssemblerUtils.h"
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#include "LlvmState.h"
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#include "MCInstrDescView.h"
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#include "ParallelSnippetGenerator.h"
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#include "RISCVInstrInfo.h"
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#include "RegisterAliasing.h"
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#include "SerialSnippetGenerator.h"
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#include "TestBase.h"
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namespace llvm {
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namespace exegesis {
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namespace {
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using testing::AnyOf;
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using testing::ElementsAre;
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using testing::HasSubstr;
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using testing::SizeIs;
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MATCHER(IsInvalid, "") { return !arg.isValid(); }
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MATCHER(IsReg, "") { return arg.isReg(); }
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template <typename SnippetGeneratorT>
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class RISCVSnippetGeneratorTest : public RISCVTestBase {
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protected:
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RISCVSnippetGeneratorTest() : Generator(State, SnippetGenerator::Options()) {}
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std::vector<CodeTemplate> checkAndGetCodeTemplates(unsigned Opcode) {
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randomGenerator().seed(0); // Initialize seed.
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const Instruction &Instr = State.getIC().getInstr(Opcode);
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auto CodeTemplateOrError = Generator.generateCodeTemplates(
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&Instr, State.getRATC().emptyRegisters());
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EXPECT_FALSE(CodeTemplateOrError.takeError()); // Valid configuration.
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return std::move(CodeTemplateOrError.get());
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}
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SnippetGeneratorT Generator;
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};
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using RISCVSerialSnippetGeneratorTest =
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RISCVSnippetGeneratorTest<SerialSnippetGenerator>;
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using RISCVParallelSnippetGeneratorTest =
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RISCVSnippetGeneratorTest<ParallelSnippetGenerator>;
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TEST_F(RISCVSerialSnippetGeneratorTest,
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ImplicitSelfDependencyThroughExplicitRegs) {
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// - ADD
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// - Op0 Explicit Def RegClass(GPR)
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// - Op1 Explicit Use RegClass(GPR)
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// - Op2 Explicit Use RegClass(GPR)
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// - Var0 [Op0]
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// - Var1 [Op1]
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// - Var2 [Op2]
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// - hasAliasingRegisters
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const unsigned Opcode = RISCV::ADD;
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const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
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ASSERT_THAT(CodeTemplates, SizeIs(1));
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const auto &CT = CodeTemplates[0];
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EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_EXPLICIT_REGS);
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ASSERT_THAT(CT.Instructions, SizeIs(1));
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const InstructionTemplate &IT = CT.Instructions[0];
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EXPECT_THAT(IT.getOpcode(), Opcode);
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ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
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EXPECT_THAT(IT.getVariableValues(),
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AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()),
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ElementsAre(IsReg(), IsReg(), IsInvalid())))
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<< "Op0 is either set to Op1 or to Op2";
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}
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TEST_F(RISCVSerialSnippetGeneratorTest,
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ImplicitSelfDependencyThroughExplicitRegsForbidAll) {
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// - XOR
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// - Op0 Explicit Def RegClass(GPR)
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// - Op1 Explicit Use RegClass(GPR)
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// - Op2 Explicit Use RegClass(GPR)
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// - Var0 [Op0]
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// - Var1 [Op1]
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// - Var2 [Op2]
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// - hasAliasingRegisters
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randomGenerator().seed(0); // Initialize seed.
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const Instruction &Instr = State.getIC().getInstr(RISCV::XOR);
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auto AllRegisters = State.getRATC().emptyRegisters();
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AllRegisters.flip();
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EXPECT_TRUE(errorToBool(
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Generator.generateCodeTemplates(&Instr, AllRegisters).takeError()));
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}
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TEST_F(RISCVParallelSnippetGeneratorTest, MemoryUse) {
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// LB reads from memory.
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// - LB
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// - Op0 Explicit Def RegClass(GPR)
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// - Op1 Explicit Use Memory RegClass(GPR)
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// - Op2 Explicit Use Memory
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// - Var0 [Op0]
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// - Var1 [Op1]
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// - Var2 [Op2]
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// - hasMemoryOperands
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const unsigned Opcode = RISCV::LB;
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const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
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ASSERT_THAT(CodeTemplates, SizeIs(1));
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const auto &CT = CodeTemplates[0];
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EXPECT_THAT(CT.Info, HasSubstr("instruction has no tied variables"));
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EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
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ASSERT_THAT(CT.Instructions,
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SizeIs(ParallelSnippetGenerator::kMinNumDifferentAddresses));
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const InstructionTemplate &IT = CT.Instructions[0];
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EXPECT_THAT(IT.getOpcode(), Opcode);
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ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
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EXPECT_EQ(IT.getVariableValues()[1].getReg(), RISCV::X10);
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}
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} // namespace
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} // namespace exegesis
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} // namespace llvm

‎llvm/unittests/tools/llvm-exegesis/RISCV/TargetTest.cpp

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//===-- TargetTest.cpp ---------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "Target.h"
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#include <cassert>
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#include <memory>
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "TestBase.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/TargetSelect.h"
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#include "gmock/gmock.h"
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#include "gtest/gtest.h"
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namespace llvm {
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namespace exegesis {
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void InitializeRISCVExegesisTarget();
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namespace {
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using testing::IsEmpty;
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using testing::Not;
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using testing::NotNull;
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class RISCVTargetTest : public RISCVTestBase {
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protected:
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std::vector<MCInst> setRegTo(unsigned Reg, const APInt &Value) {
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return State.getExegesisTarget().setRegTo(State.getSubtargetInfo(), Reg,
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Value);
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}
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};
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TEST_F(RISCVTargetTest, SetRegToConstant) {
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const auto Insts = setRegTo(RISCV::X10, APInt());
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EXPECT_THAT(Insts, Not(IsEmpty()));
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}
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} // namespace
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} // namespace exegesis
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} // namespace llvm

‎llvm/unittests/tools/llvm-exegesis/RISCV/TestBase.h

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//===-- TestBase.h ----------------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// Test fixture common to all RISC-V tests.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_UNITTESTS_TOOLS_LLVMEXEGESIS_RISCV_TESTBASE_H
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#define LLVM_UNITTESTS_TOOLS_LLVMEXEGESIS_RISCV_TESTBASE_H
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#include "LlvmState.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/TargetSelect.h"
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#include "gmock/gmock.h"
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#include "gtest/gtest.h"
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namespace llvm {
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namespace exegesis {
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void InitializeRISCVExegesisTarget();
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class RISCVTestBase : public ::testing::Test {
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protected:
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RISCVTestBase()
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: State(cantFail(
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LLVMState::Create("riscv64-unknown-linux", "generic-rv64"))) {}
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static void SetUpTestCase() {
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LLVMInitializeRISCVTargetInfo();
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LLVMInitializeRISCVTargetMC();
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LLVMInitializeRISCVTarget();
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InitializeRISCVExegesisTarget();
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}
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const LLVMState State;
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};
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} // namespace exegesis
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} // namespace llvm
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#endif

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