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Emit 64bits literal imm
1 parent 2e26b90 commit 721a622

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2 files changed

+4
-8
lines changed

2 files changed

+4
-8
lines changed

llvm/test/TableGen/riscv-target-def.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -166,9 +166,9 @@ def ROCKET : RISCVTuneProcessorModel<"rocket",
166166
// CHECK-NEXT: #define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID)
167167
// CHECK-NEXT: #endif
168168

169-
// CHECK: PROC(GENERIC_RV32, {"generic-rv32"}, {"rv32i2p1"}, 0, 0, 0x00000000, 0x00000000, 0x00000000)
169+
// CHECK: PROC(GENERIC_RV32, {"generic-rv32"}, {"rv32i2p1"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
170170
// CHECK-NEXT: PROC(GENERIC_RV64, {"generic-rv64"}, {"rv64i2p1"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
171-
// CHECK-NEXT: PROC(ROCKET_RV32, {"rocket-rv32"}, {"rv32i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0, 0x00000000, 0x00000000, 0x00000000)
171+
// CHECK-NEXT: PROC(ROCKET_RV32, {"rocket-rv32"}, {"rv32i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
172172
// CHECK-NEXT: PROC(ROCKET_RV64, {"rocket-rv64"}, {"rv64i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
173173

174174
// CHECK: #undef PROC

llvm/utils/TableGen/RISCVTargetDefEmitter.cpp

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -183,10 +183,6 @@ static void emitRISCVProcs(const RecordKeeper &RK, raw_ostream &OS) {
183183
return Feature->getValueAsString("Name") == "unaligned-vector-mem";
184184
});
185185

186-
bool IsRV64 = any_of(Features, [&](auto &Feature) {
187-
return Feature->getValueAsString("Name") == "64bit";
188-
});
189-
190186
OS << "PROC(" << Rec->getName() << ", {\"" << Rec->getValueAsString("Name")
191187
<< "\"}, {\"";
192188

@@ -205,8 +201,8 @@ static void emitRISCVProcs(const RecordKeeper &RK, raw_ostream &OS) {
205201
OS << "\"}, " << FastScalarUnalignedAccess << ", "
206202
<< FastVectorUnalignedAccess;
207203
OS << ", " << format_hex(MVendorID, 10);
208-
OS << ", " << format_hex(MArchID, IsRV64 ? 18 : 10);
209-
OS << ", " << format_hex(MImpID, IsRV64 ? 18 : 10);
204+
OS << ", " << format_hex(MArchID, 18);
205+
OS << ", " << format_hex(MImpID, 18);
210206
OS << ")\n";
211207
}
212208
OS << "\n#undef PROC\n";

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