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modify getSource for SPLAT_VECTOR
1 parent 3696f9f commit 7274170

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3 files changed

+576
-194
lines changed

3 files changed

+576
-194
lines changed

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 14 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -13597,17 +13597,27 @@ struct NodeExtensionHelper {
1359713597
case RISCVISD::VSEXT_VL:
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case RISCVISD::VZEXT_VL:
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case RISCVISD::FP_EXTEND_VL:
13600-
case ISD::SPLAT_VECTOR:
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return OrigOperand.getOperand(0);
13601+
case ISD::SPLAT_VECTOR: {
13602+
SDValue Op = OrigOperand.getOperand(0);
13603+
unsigned Opc = Op.getOpcode();
13604+
if (SupportsSExt && Opc == ISD::SIGN_EXTEND_INREG)
13605+
return Op.getOperand(0);
13606+
13607+
if (SupportsZExt && Opc == ISD::AND)
13608+
return Op.getOperand(0);
13609+
13610+
return Op;
13611+
}
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default:
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return OrigOperand;
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}
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}
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/// Check if this instance represents a splat.
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bool isSplat() const {
13609-
return (OrigOperand.getOpcode() == RISCVISD::VMV_V_X_VL) ||
13610-
(OrigOperand.getOpcode() == ISD::SPLAT_VECTOR);
13619+
return (OrigOperand.getOpcode() == RISCVISD::VMV_V_X_VL ||
13620+
OrigOperand.getOpcode() == ISD::SPLAT_VECTOR);
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}
1361213622

1361313623
/// Get the extended opcode.
@@ -13652,7 +13662,7 @@ struct NodeExtensionHelper {
1365213662
case RISCVISD::FP_EXTEND_VL:
1365313663
return DAG.getNode(ExtOpc, DL, NarrowVT, Source, Mask, VL);
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case ISD::SPLAT_VECTOR:
13655-
return DAG.getSplat(NarrowVT, DL, Source.getOperand(0));
13665+
return DAG.getSplat(NarrowVT, DL, Source);
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case RISCVISD::VMV_V_X_VL:
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return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, NarrowVT,
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DAG.getUNDEF(NarrowVT), Source.getOperand(1), VL);

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