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michaelmaitlandmichaelmaitland
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fixup! respond to review; add more tests
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+63
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2 files changed

+63
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‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1085,9 +1085,7 @@ bool RISCVLegalizerInfo::legalizeInsertSubvector(MachineInstr &MI,
10851085
// vector register or a multiple thereof, or the surrounding elements are
10861086
// undef, then this is a subvector insert which naturally aligns to a vector
10871087
// register. These can easily be handled using subregister manipulation.
1088-
if (RemIdx == 0 &&
1089-
(ExactlyVecRegSized ||
1090-
MRI.getVRegDef(BigVec)->getOpcode() == TargetOpcode::G_IMPLICIT_DEF))
1088+
if (RemIdx == 0 && ExactlyVecRegSized)
10911089
return true;
10921090

10931091
// If the subvector is smaller than a vector register, then the insertion
@@ -1123,35 +1121,37 @@ bool RISCVLegalizerInfo::legalizeInsertSubvector(MachineInstr &MI,
11231121
auto [Mask, _] = buildDefaultVLOps(BigTy, MIB, MRI);
11241122
auto VL = MIB.buildVScale(XLenTy, LitTy.getElementCount().getKnownMinValue());
11251123

1126-
// Use tail agnostic policy if we're inserting over InterLitTy's tail.
1127-
ElementCount EndIndex =
1128-
ElementCount::getScalable(RemIdx) + LitTy.getElementCount();
1129-
uint64_t Policy = RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED;
1130-
if (STI.expandVScale(EndIndex) ==
1131-
STI.expandVScale(InterLitTy.getElementCount()))
1132-
Policy = RISCVII::TAIL_AGNOSTIC;
1133-
11341124
// If we're inserting into the lowest elements, use a tail undisturbed
11351125
// vmv.v.v.
11361126
MachineInstrBuilder Inserted;
1127+
bool NeedInsertSubvec =
1128+
TypeSize::isKnownGT(BigTy.getSizeInBits(), InterLitTy.getSizeInBits());
1129+
Register InsertedDst =
1130+
NeedInsertSubvec ? MRI.createGenericVirtualRegister(InterLitTy) : Dst;
11371131
if (RemIdx == 0) {
1138-
Inserted = MIB.buildInstr(RISCV::G_VMV_V_V_VL, {InterLitTy},
1132+
Inserted = MIB.buildInstr(RISCV::G_VMV_V_V_VL, {InsertedDst},
11391133
{AlignedExtract, Insert, VL});
11401134
} else {
11411135
auto SlideupAmt = MIB.buildVScale(XLenTy, RemIdx);
11421136
// Construct the vector length corresponding to RemIdx + length(LitTy).
11431137
VL = MIB.buildAdd(XLenTy, SlideupAmt, VL);
1138+
// Use tail agnostic policy if we're inserting over InterLitTy's tail.
1139+
ElementCount EndIndex =
1140+
ElementCount::getScalable(RemIdx) + LitTy.getElementCount();
1141+
uint64_t Policy = RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED;
1142+
if (STI.expandVScale(EndIndex) ==
1143+
STI.expandVScale(InterLitTy.getElementCount()))
1144+
Policy = RISCVII::TAIL_AGNOSTIC;
1145+
11441146
Inserted =
1145-
MIB.buildInstr(RISCV::G_VSLIDEUP_VL, {InterLitTy},
1147+
MIB.buildInstr(RISCV::G_VSLIDEUP_VL, {InsertedDst},
11461148
{AlignedExtract, Insert, SlideupAmt, Mask, VL, Policy});
11471149
}
11481150

11491151
// If required, insert this subvector back into the correct vector register.
11501152
// This should resolve to an INSERT_SUBREG instruction.
1151-
if (TypeSize::isKnownGT(BigTy.getSizeInBits(), InterLitTy.getSizeInBits()))
1152-
MIB.buildInsertSubvector(Dst, BigVec, LitVec, AlignedIdx);
1153-
else
1154-
Inserted->getOperand(0).setReg(Dst);
1153+
if (NeedInsertSubvec)
1154+
MIB.buildInsertSubvector(Dst, BigVec, Inserted, AlignedIdx);
11551155

11561156
MI.eraseFromParent();
11571157
return true;

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insert-subvector.mir

Lines changed: 46 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -517,6 +517,52 @@ body: |
517517
PseudoRET implicit $v8
518518
...
519519
---
520+
name: insert_subvector_nxv8i16_nxv1i16
521+
legalized: false
522+
tracksRegLiveness: true
523+
body: |
524+
bb.0.entry:
525+
liveins: $v8m8
526+
; RV32-LABEL: name: insert_subvector_nxv8i16_nxv1i16
527+
; RV32: liveins: $v8m8
528+
; RV32-NEXT: {{ $}}
529+
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8
530+
; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF
531+
; RV32-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_EXTRACT_SUBVECTOR [[COPY]](<vscale x 8 x s16>), 4
532+
; RV32-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF
533+
; RV32-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_SUBVECTOR [[DEF1]], [[DEF]](<vscale x 1 x s16>), 0
534+
; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL $x0
535+
; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB
536+
; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
537+
; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C]](s64)
538+
; RV32-NEXT: [[VMV_V_V_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VMV_V_V_VL [[EXTRACT_SUBVECTOR]], [[INSERT_SUBVECTOR]](<vscale x 4 x s16>), [[LSHR]](s64)
539+
; RV32-NEXT: [[INSERT_SUBVECTOR1:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_SUBVECTOR [[COPY]], [[VMV_V_V_VL]](<vscale x 4 x s16>), 4
540+
; RV32-NEXT: $v8 = COPY [[INSERT_SUBVECTOR1]](<vscale x 8 x s16>)
541+
; RV32-NEXT: PseudoRET implicit $v8
542+
;
543+
; RV64-LABEL: name: insert_subvector_nxv8i16_nxv1i16
544+
; RV64: liveins: $v8m8
545+
; RV64-NEXT: {{ $}}
546+
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8
547+
; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF
548+
; RV64-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_EXTRACT_SUBVECTOR [[COPY]](<vscale x 8 x s16>), 4
549+
; RV64-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF
550+
; RV64-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_SUBVECTOR [[DEF1]], [[DEF]](<vscale x 1 x s16>), 0
551+
; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL $x0
552+
; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
553+
; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
554+
; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
555+
; RV64-NEXT: [[VMV_V_V_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VMV_V_V_VL [[EXTRACT_SUBVECTOR]], [[INSERT_SUBVECTOR]](<vscale x 4 x s16>), [[LSHR]](s32)
556+
; RV64-NEXT: [[INSERT_SUBVECTOR1:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_SUBVECTOR [[COPY]], [[VMV_V_V_VL]](<vscale x 4 x s16>), 4
557+
; RV64-NEXT: $v8 = COPY [[INSERT_SUBVECTOR1]](<vscale x 8 x s16>)
558+
; RV64-NEXT: PseudoRET implicit $v8
559+
%0:_(<vscale x 8 x s16>) = COPY $v8
560+
%1:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF
561+
%2:_(<vscale x 8 x s16>) = G_INSERT_SUBVECTOR %0(<vscale x 8 x s16>), %1, 4
562+
$v8 = COPY %2(<vscale x 8 x s16>)
563+
PseudoRET implicit $v8
564+
...
565+
---
520566
name: insert_subvector_nxv4i32_nxv8i32
521567
legalized: false
522568
tracksRegLiveness: true

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